Questions tagged [cortex-m]
For all ARM Cortex-M series cores, including M0, M0+, M1, M3, M4, M7, M23 and M33.
cortex-m
1,415
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How to correctly implement delay after enabling RCC peripheral clock?
I'm new to STM32 microcontrollers. I would like to know how to correctly implement 2-clock-cycle delay after enabling RCC peripheral clock.
Section 5.2.16 (page# 134) of https://www.st.com/resource/en/...
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2
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0
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78
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Embedded C++ - Header-only library optimization level
I mainly develop firmware for ARM Cortex M using gcc and I am migrating from C to C++ and even though I am overall happy with the transition, there are some things that I just can't get right.
...
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Build valgrind to target LPC55S69(which is based on Armv8-m architecture)
I'm trying to build valgrind to target baremetal arm cortex-m (based on armv8-m architecture). The host is a x86 wsl environment. How do I specify this while trying to configure valgrind.
For ex: To ...
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1
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34
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ARM Cortex-M Trustzone (ab)use to isolate third party application
I am new to trustzone on the Cortex-M and am wondering if I can use it to isolate a third party application from a bunch of legacy code.
The idea would be to move the legacy code with freertos into ...
- 4,949
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16
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VSCode Arduino environment, SAMD51J19A, persistent DummyHandlers
I've been developing an embedded application for months for an Adafruit Feather M4 Express board. I'm using the VSCode Arduino environment, and it's been going well, up until:
After putting down the ...
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0
answers
11
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How to determine if interrupts are enabled Arm Cortex M4F (STM32G44)
I have a function that is called when the interrupts are enable and other times when disabled and it must behave different depending on the interrupt enabled state.
I reviewed the reference manual but ...
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2
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43
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Can I service the SysTick interrupt while already in HSEM interrupt (STM32H745, M4 core)?
I have a situation where my software enters a HSEM interrupt (with the M4 core) and while it is servicing that interrupt it is ignoring the SysTick interrupt. Exiting the HSEM interrupt is dependent ...
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33
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Ho to use CMSIS-Core (Cortex-M) for TM4C123GH6PM and TM4C129ENCPDT in Code Composer Studio
I'm trying to write drivers for TM4C129ENCPDT and TM4C123GH6PM in Code Composer Studio(Linux). I prefer to use CMSIS and not Tivaware. I'm unable to get the CMSIS-Core Device Files (provided by ...
- 9
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14
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Can't find the 'No Access' permission in Cortex M55 MPU
I'm trying to configure the MPU region, but I can't find the 'No Access' permission.
There are only Read/Write permission.
How can I configure a memory region to 'No Access' in Cortex M55?
I read a ...
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39
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Analyzing Relocations in ARM for cortex-m4
I'm trying to understand how to correctly read the relocation entries generated by my ARM compiler (I'm using (GNU Arm Embedded Toolchain 9-2020-q2-update) 9.3.1 20200408 (release)).
To my ...
- 3
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Position-Indipendent FW for Cortex M
Due to a educational requirement, I need to write a FW that can be run in RAM at non-predetermined locations.
First of all I don't know which gcc parameters are needed, although I think it's either -...
- 1,408
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How TBB and DCB work in branching the flow?
I am new to ARM Cortex and facing difficulty to understand how TBB branches.
Code snippet attached:
TBB [PC,R1]
BrTable1
DCB ((P0 - BrTable1)/2)
DCB ((P1 - BrTable1)/2)
Now, my understanding is as ...
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1
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61
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ARM GCC fails to create a working binary for STM32F4, lot of discarded code
I've been migrating all my STM32 projects to Codeblocks IDE and GCC compiler (arm-none-eabi).
The process is using STM's CubeMX to generate the base code, then merge everything to a proper folder with ...
- 11
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48
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Creating C labels to be used by inline assembly for CORTEX-M
I need to write some inline assembly code embedded in C, the code containts some looping. I do not want to create a separate .s file for the assembly code as that would mean I modify some compile ...
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31
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MPU protected region not protected against EEFC_FCR ES erasure (cortex m4)
I set up an MPU region on a Cortex-M4 with AP encoding 000 (no access),
MPU->RBAR = address | (1 << 4) | (1 << 0);
MPU->RASR = (1 << 17) | (1 << 3) | (1 << 0);
MPU-&...
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