All Questions
273
questions
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52
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Local variable allocation crashes the stack in embedded C on cortexm4 and operating system
Details: embedded C, cortex M4 with operating system (RTX Kernel), compiled with ARM Compiler V5.06 update6 and Microlib.
Inside a periodic task there are some functons call, one is a debug function:
/...
- 315
0
votes
1
answer
22
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Is the libsnark library compatible with the arm-none-eabi toolchain for ARM Cortex-M microcontrollers?
I am currently working on a project that involves implementing cryptographic protocols on ARM Cortex-M microcontrollers, specifically the Raspberry Pi Pico (RP2040). I am interested in using the ...
0
votes
1
answer
41
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Taking FreeRTOS as an example, how to separate the kernel from the application? (Physical)
enter image description hereBackground: FreeRTOS, Cortext-M3
Suppose there is a situation where the kernel and application are developed separately, and the .text segment of the kernel and the ...
1
vote
1
answer
103
views
How to correctly implement delay after enabling RCC peripheral clock?
I'm new to STM32 microcontrollers. I would like to know how to correctly implement 2-clock-cycle delay after enabling RCC peripheral clock.
Section 5.2.16 (page# 134) of https://www.st.com/resource/en/...
- 559
2
votes
0
answers
82
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Embedded C++ - Header-only library optimization level
I mainly develop firmware for ARM Cortex M using gcc and I am migrating from C to C++ and even though I am overall happy with the transition, there are some things that I just can't get right.
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- 31
0
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1
answer
34
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MPU protected region not protected against EEFC_FCR ES erasure (cortex m4)
I set up an MPU region on a Cortex-M4 with AP encoding 000 (no access),
MPU->RBAR = address | (1 << 4) | (1 << 0);
MPU->RASR = (1 << 17) | (1 << 3) | (1 << 0);
MPU-&...
- 73
0
votes
3
answers
167
views
How to perform a MCU reset after a specific hardfault?
As I didn't find an existing questions on stackoverflow or on google, please find the context below.
I'm investigating an issue leading to 2 different hardfaults on ARM Cortex-M33.
The first one ...
- 520
0
votes
1
answer
77
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Unable to read value from gpio set as input
I am working on a custom board with two IMX7ULP. The thing I'm trying to do seems quite simple, the A7 from one IMX7ULP send a signal to the M4 of the other IMX7ULP, just an electrical signal, one of ...
- 1
0
votes
1
answer
88
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Can't connect ST-Link with APM32F003 through OpenOCD
I'm using CLion and try to debug my APM32F003 base project with ST-Link.
I cannot determine what the problem is with ST-Link.
I'm using Geehy's OpenOCD build with APM32F003 config files.
My project ...
- 31
-1
votes
1
answer
56
views
Cortex-M external interrupt occurs when executing fault handler with higher priority
What happens when a lower priority interrupt from a peripheral occurs while the cortex-m is executing a higher priority fault handler? Will it be ignored or will it trigger a hardfault?
0
votes
3
answers
127
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How to do unaligned int store on ARM Cortex M4? [duplicate]
How can C code take advantage of the Cortex M4's unaligned 4-byte store instruction?
*(int*)p = x mostly works, but occasionally I end up with something like this:
void Store(uint8_t* p, uint32_t a, ...
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0
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0
answers
142
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I cant get my thread context switching code to work (ARM procesor)
Im developing a "operating system" on ARM. My context switching code for swapping between tasks is not working.
I have a function demo() which I am calling in main. In this I am creating a &...
0
votes
0
answers
54
views
writing and reading from the same memory address from two different QEMU instances
I have a code to write "Hello" at the memory address 0x10000000, and another code to read the value from this memory address and print it out. I have defined 0x10000000 as a shared memory in ...
- 1
0
votes
1
answer
690
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Heap and Stack allocation in ThreadX RTOS
Recently I started learning ThreadX RTOS and I noticed that in the linker script and crt0.S provided for Cortex-M4 with gcc toolchain, .stack and .heap sections are allocated with size 1024 bytes and ...
0
votes
0
answers
56
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i.MX8MP: Which .dts file addresses are accessible to both processors at once?
Which of these memory areas can be used simultaneously by two cores - Cortex M7 and Cortex A53? And how can I do this? What address do I need to specify for the mmap function on the Linux side so that ...
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