All Questions
24
questions
2
votes
0
answers
50
views
ARM Cortex M4 context switching: How does the hardware know where xPSR, PC, LR, R12, R3-R0 are on the stack?
I'm working on a context switching mechanism for my RTOS which runs on Cortex-Ms.
When I initialize a task's stack, I have it like this
Then, I decrement the stack pointer 8 times to fit R11-R4.
I ...
- 33
0
votes
1
answer
41
views
Taking FreeRTOS as an example, how to separate the kernel from the application? (Physical)
enter image description hereBackground: FreeRTOS, Cortext-M3
Suppose there is a situation where the kernel and application are developed separately, and the .text segment of the kernel and the ...
0
votes
1
answer
689
views
Heap and Stack allocation in ThreadX RTOS
Recently I started learning ThreadX RTOS and I noticed that in the linker script and crt0.S provided for Cortex-M4 with gcc toolchain, .stack and .heap sections are allocated with size 1024 bytes and ...
0
votes
1
answer
39
views
MSP stack overflow on Cortex-M4 running UCOS-II RTOS
I am using UCOS-II, the underlying operating system for my project. Now, I have encountered a problem that is very difficult for me. I hope someone can give me some advice.
I'm running it on a Cortex-...
- 21
0
votes
2
answers
1k
views
Process stacks and interrupts on Cortex-M ARM cores
According to ARMv7-M and ARMv8-M reference manuals, exception stack frame is formed on currently active stack (MSP or PSP, depending on what was interrupted by the exception).
This decision looks ...
- 1,219
0
votes
0
answers
110
views
Tiva C TM4C123GXL digital outputs problem
I didn't find the same problem like my anywhere, but I hope someone have any advices what happenin with my uC.
Digital outputs are very "sensitive / delicate". Namely, I have connected PC4-...
- 1
2
votes
1
answer
407
views
ARM GCC + Cortex M4: Calling address as function generates BLX instead of BL
I build as little OS for a CortexM4 CPU which is able to receive compiled binaries over UART and schedule them dynamically. I want to use that feature to craft a testsuite which uploads test programs ...
- 89
0
votes
1
answer
616
views
Azure RTOS ThreadX with STM32L476VG
I would like to install threadX on a STM32L476VG. I am quite new to RTOS programming.
As I set up some simple applications I run into a HardFault whenever I called the tx_thread_resume function within ...
0
votes
1
answer
132
views
Cortex-M3 SysTick double interrupt
I'm creating a rtos system, with system tick (1ms) for real-time and trigger pendsv-which used for switch task. Priority of systick and pendsv same as 0 (group = 16; <SCB.AIRCR.PRIGROUP = 0b011>)...
0
votes
0
answers
380
views
My threads don't appear on Keil uvision's RTOS watch
I'm using Keil uVision with RTX5 RTOS and for some reason I can't see the threads I'm creating in the RTOS watch... I can only see the built in RTX idle thread and timer thread...
I've tested that my ...
3
votes
4
answers
3k
views
How to run a periodic thread in high frequency(> 100kHz) in a Cortex-M3 microcontroller in an RTOS?
I'm implementing a high frequency(>100kHz) Data acquisition system with an STM32F107VC microcontroller. It uses the spi peripheral to communicate with a high frequency ADC chip. I have to use an RTOS. ...
0
votes
0
answers
112
views
Operating systems for MCUs that use system calls to abstract away interaction with device peripherals
This question is a reference request.
Typical embedded operating systems like mbedOS or FreeRTOS don't use system calls (e.g. supervisor calls in ARM cores), or only use them to provide a very small ...
- 1,012
2
votes
1
answer
2k
views
ARM Cortex M4 - What happens to SysTick interrupt request when PRIMASK is set to 1?
I'm learning about RTOS and I'm at a section talking about Semaphores. The book implements a spin-lock semaphore, but I'm having trouble understanding what happens with SysTick, which is used to ...
- 55
0
votes
1
answer
325
views
STM32 RTX Usage Fault PSP 0x00000020
I have a project with an STM32F446, with RTX, 3 threads (main + 2 declared by me) + of course the idle one. The main thread enters wait state after starting the two threads so i have just two threads ...
- 3
2
votes
2
answers
10k
views
'Usage fault exception' in ARM Cortex M
I attended a lecture on FreeRtos and Cortex M where the instructor advised that if ISR safe version of API is not used from ISR it can lead to Usage fault exception in Cortex M processors.This would ...
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