Questions tagged [thumb]
A reduced instruction set for ARM processors (based on a 16-bit encoding, instead of 32 bits in standard ARM mode), originally intended for embedded systems with a small amount of RAM. Also for question with the later Thumb2 mixed 16 and 32 bit instruction modes. Consider the tags 'slider' and 'thumbnails' for other meanings of 'thumb'.
thumb
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Ways to perform bitwise operations with symbols inside Assembly constants?
I am working on learning to write ARM firmware and am trying to create a Vector Table. I am using the GNU toolchain.
I have assembly code like the following:
MY_VECTOR_TABLE:
.long 0 ...
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How TBB and DCB work in branching the flow?
I am new to ARM Cortex and facing difficulty to understand how TBB branches.
Code snippet attached:
TBB [PC,R1]
BrTable1
DCB ((P0 - BrTable1)/2)
DCB ((P1 - BrTable1)/2)
Now, my understanding is as ...
1
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1
answer
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Mysterious ARM Opcode
In decompiling a hex file for a Texas Instruments ARM (Thumb 2) Cortex-M4f processor (CC2652RB), I have come across an opcode that I can't figure out.
What does "90 FF FF 00" do (maybe the ...
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How is this ARM (Thumb) LDR Instruction being calculated?
The code is running on a Cortex M0+. I am trying to calculate the addresses of LDR PC-related loads and am finding the addresses are not always consistent.
This LDR PC-related load does not follow ...
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Which instruction encoding is supported by a ARM processor, particularly a Cortex M0, STM32F0 one for example
Confused about instruction encoding supported by my core (ie. T1, T2, etc)
Having the STM32F0 series Cortex-M0 programming manual, I found that
https://www.st.com/resource/en/programming_manual/pm0215-...
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Why the Link register in FIQ mode will be instruction address plus 4 in thumb mode instead of instruction address plus 2?
I am going through the Cortex R5 technical reference manual (version: r1p2). And according to the manual the
LR_SVC will have IA + 4 in ARM mode and IA+2 in Thumb mode, which I can understand since ...
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1
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gcc inline asm / constraints / "r" relates to "l" like "g" to ...?
I'm trying to compile this for an ARM Cortex-M0+ (STM32G030) with arm-none-eabi-gcc:
asm("ldrb %0, [%1, %2]\n" : "=l" (v) : "l" (R.a+(o&~31)) , "g" (o&...
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Loading a the address of a pointer into a register inline thumb assembly
I'm trying to read in the address from my c-pointer to a register using inline thumb assembly.
here's a reproducible:
static uint32_t volatile * volatile CurrentTaskStackPtr;
CurrentTaskStackPtr = (...
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1
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Inline version of function fails
I've been writing code to interface with a hardware register on SAMV71Q20B. The function in question is:
// Reads current MII link busy status
u32 mii_is_busy(void)
{
return !GMAC->GMAC_NSR....
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2
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How does the arm-none-eabi-as choose section alignment?
I am playing with arm-none-eabi-as trying to understand how it aligns sections. I have the following source:
; source.s
.text
.byte 0xff
.byte 0xff
.byte 0xff
I am inspecting the resulting object ...
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1
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How to Properly Handle the LR Register in an Interrupt Service Routine for Thumb Mode on ARM? [closed]
When ARM chips（cortex-A7）are compiled in thumb mode, the program may run abnormally, and the exception point has been located. The problematic C code is:
while (locked && result)
{
// ...
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1
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Compare signed integers and return either 0 or -1 in Thumb2 assembly
In thumb2 assembly, when r0 and r1 have signed integers, I like to have r1=-1 (i.e. 0xffffffff) if r0 < r1, otherwise r1=0.
I can simply code:
4288 cmp r0, r1
bfb4 ite ...
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2
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Assembler Thumb Mode
im new in coding with Assembler and I have a question concerning the .thumb and .Syntax unified directive. I know there is a instruction set "Thumb", which contains 16-Bit commands, the ...
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STM32 sometimes hardfault on reboot (thumb instruction issue?)
STM32L496 micro is hard faulting when power is cycled, but only on some builds of firmware, others are ok. I've been able to track it down to a specific path in the assembly, what looks like is ...
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Can I force a Cortex-M4 ARM processor to use conditional instructions outside an IT block?
I need to profile different machine instruction for a project, so I'm running some instructions in a loop of ~200 instructions per time (using .rept in an __asm__ directive). The processor I'm using ...
