All Questions
219
questions
2
votes
0
answers
50
views
ARM Cortex M4 context switching: How does the hardware know where xPSR, PC, LR, R12, R3-R0 are on the stack?
I'm working on a context switching mechanism for my RTOS which runs on Cortex-Ms.
When I initialize a task's stack, I have it like this
Then, I decrement the stack pointer 8 times to fit R11-R4.
I ...
- 33
0
votes
1
answer
35
views
Can i boot from sram when i use arm cortex m3
normally,we boot from flash or ROM, but what if i want to boot from SRAM area(0x20000000_0x3fffffff) instead of Code area(0x00000000_0x1fffffff), should i use startup.s to copy the code to SRAM area?
...
0
votes
0
answers
32
views
How TBB and DCB work in branching the flow?
I am new to ARM Cortex and facing difficulty to understand how TBB branches.
Code snippet attached:
TBB [PC,R1]
BrTable1
DCB ((P0 - BrTable1)/2)
DCB ((P1 - BrTable1)/2)
Now, my understanding is as ...
6
votes
2
answers
226
views
Issue with measuring ARM MCU interrupt latency
Introduction
I am a student who wants to roughly measure the interrupt latency of ARM Cortex-M series chips without using an oscilloscope. However, I have encountered a very peculiar issue that has ...
- 73
1
vote
1
answer
62
views
What is the most efficient way to write two (for example) bits of a register using cortex-m0 instruction set?
Simple example. We want to write '01' bits in the most right bits of register.
Should we reset '0' bit and set '1' bit separately? Is there a way to do it in a single instruction?
For instance, if the ...
- 27
-1
votes
1
answer
129
views
Can somebody translate this ASM instruction code for Cortex M7?
" mrs %0, ipsr " : "=r" (reg_tmp)
I need to translate this ASM code out-of-curiosity, it is for ARMV7 specifically cortex-M7 executing in privileged mode. I know MRS instruction ...
- 55
-1
votes
1
answer
177
views
Arm cortex m0 LDR instruction
What is the difference between these instructions in the ARM Cortex M0?
LDR r1, r2
LDR r1, [r2]
MOV r1, r2
Is any of them wrong?
If none of them is wrong, why would I use the second one to load from ...
0
votes
0
answers
136
views
Which instruction encoding is supported by a ARM processor, particularly a Cortex M0, STM32F0 one for example
Confused about instruction encoding supported by my core (ie. T1, T2, etc)
Having the STM32F0 series Cortex-M0 programming manual, I found that
https://www.st.com/resource/en/programming_manual/pm0215-...
- 1,609
2
votes
1
answer
352
views
Program Status Registers ARM Cortex-M4
I would like some help understanding the program status register.
I have a couple simple instructions below to test what will happen to the xPSR.
After I execute adds r0,r1 my xPSR is:
...
2
votes
0
answers
146
views
Cortex M-4 Arm processor mov / movt / movw
I was hoping to get some clarification on something that I’m having trouble understanding.
I am using cortex-m processor with gnu assembler and I’m trying to put 0x1A2B3F4C into r0.
In the book that I’...
0
votes
1
answer
542
views
How to read a GPIO input pin in ARM using the Raspberry Pi Pico?
I am starting to learn assembly language and ARM using the raspberry pi pico.
I have even been following the book RP2040 Assembly Language programming but there is no instruction about how to read an ...
2
votes
0
answers
92
views
lib gcc _init() function executing address as instruction
Compiling with gcc-arm-none-eabi and default libc for a cortex M4 target will result in an _init() function that executes a memory location as if it was an isntruction. Dissasembly of the _()init is:
...
- 21
0
votes
1
answer
80
views
Why can't I assemble this single FPU instruction with GNU as?
I'm trying to retrieve the binary representation of a few FPU instructions for the Cortex-M4 processor. I resolved to put the code I need to retrieve in a file like this
.syntax unified
vsub.f32 s0, ...
1
vote
0
answers
89
views
Cortex-M4: LDRD or VLDR.64 to move uint64_t
The following code produces
volatile uint64_t x1;
volatile uint64_t x3;
int main(){
while(true) {
x3 = x1;
}
}
uses LDRD/STRD to transfer the double word. In outher situations, where ...
- 5,292
0
votes
0
answers
78
views
How can I implement Read/Modify/Write for Microcomputer Peripheral Registers without Bitbanding?
I want to know how to implement Read/Modify/Write againt Microcomputer Peripheral Register.
For example, UART control and status register.
When I turn off UART interrupt enable flag, I read/modify/...
- 1