All Questions
803
questions
2
votes
0
answers
50
views
ARM Cortex M4 context switching: How does the hardware know where xPSR, PC, LR, R12, R3-R0 are on the stack?
I'm working on a context switching mechanism for my RTOS which runs on Cortex-Ms.
When I initialize a task's stack, I have it like this
Then, I decrement the stack pointer 8 times to fit R11-R4.
I ...
- 33
0
votes
1
answer
22
views
Is the libsnark library compatible with the arm-none-eabi toolchain for ARM Cortex-M microcontrollers?
I am currently working on a project that involves implementing cryptographic protocols on ARM Cortex-M microcontrollers, specifically the Raspberry Pi Pico (RP2040). I am interested in using the ...
0
votes
1
answer
35
views
Can i boot from sram when i use arm cortex m3
normally,we boot from flash or ROM, but what if i want to boot from SRAM area(0x20000000_0x3fffffff) instead of Code area(0x00000000_0x1fffffff), should i use startup.s to copy the code to SRAM area?
...
0
votes
0
answers
47
views
Unwinding Stack on Cortex-M with FreeRTOS: Handling Interrupts and Stopping Conditions
I am writing an unwinder for a Cortex-M (an ARM processor) running FreeRTOS. It mostly works, and I can trace the stack in many cases, but I have encountered a few issues that I haven't been able to ...
1
vote
1
answer
52
views
How/When exactly does Cortex-M4 (STM32 F4) switch its R13 from MSP to PSP? Do i have to manually switch if using PSP in inline asm?
I'm writing my own RTOS and I'm implementing the context switch function, where I have to use PSP. The function is written in inline assembly
I was working on another project on STM32 F4 writing ...
- 33
1
vote
1
answer
103
views
How to correctly implement delay after enabling RCC peripheral clock?
I'm new to STM32 microcontrollers. I would like to know how to correctly implement 2-clock-cycle delay after enabling RCC peripheral clock.
Section 5.2.16 (page# 134) of https://www.st.com/resource/en/...
- 559
0
votes
0
answers
27
views
Build valgrind to target LPC55S69(which is based on Armv8-m architecture)
I'm trying to build valgrind to target baremetal arm cortex-m (based on armv8-m architecture). The host is a x86 wsl environment. How do I specify this while trying to configure valgrind.
For ex: To ...
0
votes
1
answer
37
views
ARM Cortex-M Trustzone (ab)use to isolate third party application
I am new to trustzone on the Cortex-M and am wondering if I can use it to isolate a third party application from a bunch of legacy code.
The idea would be to move the legacy code with freertos into ...
- 4,949
0
votes
0
answers
35
views
Ho to use CMSIS-Core (Cortex-M) for TM4C123GH6PM and TM4C129ENCPDT in Code Composer Studio
I'm trying to write drivers for TM4C129ENCPDT and TM4C123GH6PM in Code Composer Studio(Linux). I prefer to use CMSIS and not Tivaware. I'm unable to get the CMSIS-Core Device Files (provided by ...
- 9
0
votes
1
answer
42
views
Analyzing Relocations in ARM for cortex-m4
I'm trying to understand how to correctly read the relocation entries generated by my ARM compiler (I'm using (GNU Arm Embedded Toolchain 9-2020-q2-update) 9.3.1 20200408 (release)).
To my ...
- 3
0
votes
0
answers
32
views
How TBB and DCB work in branching the flow?
I am new to ARM Cortex and facing difficulty to understand how TBB branches.
Code snippet attached:
TBB [PC,R1]
BrTable1
DCB ((P0 - BrTable1)/2)
DCB ((P1 - BrTable1)/2)
Now, my understanding is as ...
0
votes
1
answer
63
views
ARM GCC fails to create a working binary for STM32F4, lot of discarded code
I've been migrating all my STM32 projects to Codeblocks IDE and GCC compiler (arm-none-eabi).
The process is using STM's CubeMX to generate the base code, then merge everything to a proper folder with ...
- 11
0
votes
1
answer
34
views
MPU protected region not protected against EEFC_FCR ES erasure (cortex m4)
I set up an MPU region on a Cortex-M4 with AP encoding 000 (no access),
MPU->RBAR = address | (1 << 4) | (1 << 0);
MPU->RASR = (1 << 17) | (1 << 3) | (1 << 0);
MPU-&...
- 73
1
vote
0
answers
48
views
MCU SysTick infinite loop
During the development of an embedded device, I encountered a one time bug with no interruptions working. It's important to understand that this device usually works fine, and has been for a few years ...
- 43
1
vote
1
answer
171
views
ARM Cortex-M PC and SP values - reset behavior
I am trying to understand the ARM cortex-M hardware behavior on reset; particularly how the SP and PC values are written upon a cold start or hard reset.
Basically, it would seem the hardware (aka PE ...
- 11