All Questions
Tagged with cortex-m inline-assembly
24
questions
-1
votes
1
answer
129
views
Can somebody translate this ASM instruction code for Cortex M7?
" mrs %0, ipsr " : "=r" (reg_tmp)
I need to translate this ASM code out-of-curiosity, it is for ARMV7 specifically cortex-M7 executing in privileged mode. I know MRS instruction ...
- 55
0
votes
1
answer
148
views
gcc, arm, inline assembly, BX produce unexpected results trying to jump over a goto section
I am using Cortex M0+;
I am trying to preserve a piece of code inside the regular code flow, don't ask me why :)
Basically later on, I'd like to jump to MYCODE.
This is the code
bool x = false; // ...
- 1,609
1
vote
1
answer
372
views
Cortex M4 SVC code appears to always pass in 255 for the SVC number
I've tried following the documentation to make an SVC instruction work. From the Arm documentation here my SVC_Handler function is as they specify:
void SVC_Handler(void)
{
__asm(
".global ...
1
vote
1
answer
698
views
Inserting inline assembly code into C function - I/O questions
I am developing an embedded C application for my Cortex M3 microcontroller using the GNU arm-none-eabi toolchain.
I have plan to adopt an assembly subroutine that the vendor implemented into my C ...
- 23
2
votes
1
answer
357
views
Can I force a Cortex-M4 ARM processor to use conditional instructions outside an IT block?
I need to profile different machine instruction for a project, so I'm running some instructions in a loop of ~200 instructions per time (using .rept in an __asm__ directive). The processor I'm using ...
0
votes
1
answer
316
views
Why I got this "Error[Ta087]: Register r8 not available to clobber in selected core/mode" on IAR EWARM
I am trying to compile an IAR project with mixed C and ASM for Cortex-M0, and I got an error of
Error[Ta087]: Register r8 not available to clobber in selected
core/mode
when I have this line
: "...
- 23
0
votes
1
answer
787
views
How do I access a local variable using ARM assembly language?
I use the following piece of assembly code to enter the critical section in ARM Cortex-M4.
The question is, how can I access the local variable primeMask?
volatile uint8_t primaskValue; ...
- 11
0
votes
0
answers
129
views
Solve Cortex M7 priority inversion deadlock by surrendering context from a higher priority IRQ to a lower priority IRQ
Background
I have a custom bare metal mutex primitive written for the STM32F7 (Arm Cortex M7) processor per the Barrier and Litmus Test Cookbook from ARM, using the LDREX and STREX instructions. I use ...
- 113
1
vote
1
answer
919
views
How to pass function address to Assembler Instructions with C Expression Operands
With gcc/clang for ARM cortex M, is there a way to pass a function address as a constant in Assembler Instructions with C Expression Operands ? More precisely I'd like to load R12 with function ...
- 147
1
vote
2
answers
777
views
How to mark as clobbered input operands (C register variables) in extended GCC inline assembly?
Problem description
I'm trying to design the C code unpacking array A of uint32_t elements to array B of uint32_t elements where each element of A is unpacked to two consecutive elements of B so that ...
- 13
0
votes
1
answer
3k
views
How to do 64 bit division in ARM cortex M3 device
I want to divide 64 bit number by 32 bit number in ARM cortex M3 device using ARM inline assembler.
I tried dividing 32 bit number by 32 bit number, its working fine. I shared the code also. Please ...
- 13
0
votes
0
answers
452
views
Correctly passing arguments to supervisor calls with GCC [duplicate]
I'm using the following code to generate supervisor calls:
#define SVC(code) __asm__ volatile ("svc %0" : : "I" (code))
void svc_rgb(uint8_t red, uint8_t green, uint8_t blue) {
SVC(7);
}
int ...
- 1,012
4
votes
2
answers
2k
views
Calling a C function from ARM function defined with __asm
I am having trouble understanding my compiler. We use the Scons utility to compile ARM code for an M0+ processor (on Windows, if it matters. It's an ARMCC compile) I am trying to capture the address ...
- 184
0
votes
3
answers
1k
views
Branching to a c symbol from thumb inline assembly
I'm on a Cortex-M0+ device (Thumb only) and I'm trying to dynamically generate some code in ram and then jump to it, like so:
uint16_t code_buf[18];
...
void jump() {
register volatile uint32_t* ...
- 194
5
votes
2
answers
856
views
What is the correct way to tell the compiler that I want a variable to be always stored in a register?
Reading the answers of this question it came to my attention that register is no longer a valid storage specifier in C++17. Some comments even suggest that the compiler had already ignored register ...
- 18.9k