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Questions tagged [cortex-m]

For all ARM Cortex-M series cores, including M0, M0+, M1, M3, M4, M7, M23 and M33.

cortex-m
455 questions with no upvoted or accepted answers
4 votes
0 answers
3k views

Debugging STM32 with OpenOCD, STM32 for VSCODE won't work or flash, Configuration issue maybe?

First and for most I googled a lot and Its been a week of searching with no solution at all. Please bare with me! I tried to add all necessary info! Please request more If you need. My problem is: I ...
The_M_Code's user avatar
4 votes
0 answers
569 views

Backtrace full of duplicate entries when debugging Rust firmware for STM32 with ARM GDB

What am I doing I'm trying to use Rust to make a firmware for STM32F103 board and debug it using GDB. My project more or less follows blinky.rs example from https://github.com/stm32-rs/stm32f1xx-hal ...
SuperPrower's user avatar
4 votes
1 answer
2k views

ARM Cortex M detect if debugger is in Run or Debug mode

There is a proven way to detect whether a debugger is connected on Cortex-M, as seen here. I used to as a way to automatically set a breakpoint when I am in a debug session: void autobreak() { if (...
Ken Lin's user avatar
  • 1,015
4 votes
0 answers
1k views

how to see memory layout of struct, class object

I'm on an embedded system and need to wring out an additional couple dozen bytes from the heap. Once I've built the .elf, is there a utility to run so I can output the memory layout of my class ...
Bob's user avatar
  • 4,860
4 votes
1 answer
4k views

STM32H7xx toggle IO as fast as possible

I'm trying to toggle an IO on an STM32H743 as fast as possible. I'm using an external 10MHz clock, powered at 3.3V, and I'm confident my main clock is running at 400MHz and the bus clock that talks to ...
Jotux's user avatar
  • 157
3 votes
1 answer
376 views

debugging two cortex elf files (bootloader and application)

I have an STM microcontroller and trying to use VS Code to use a debugger for the bootloader and application. I have a launch configuration for each, but after launching the bootloader, I can't ...
lordhog's user avatar
  • 3,597
3 votes
0 answers
994 views

xQueueReceive blocks the execution of other tasks

I am developing a FreeRTOS application on a Cortex-M4 (NXP i.MX8MM) that creates 4 tasks. The first task is waiting to receive a character on a UART. As soon as a buffer is received, it is sent to ...
Martin Denion's user avatar
3 votes
0 answers
272 views

GCC, GDB, and is_stmt

I'm using GNU Arm Embedded Toolchain 10.3 to cross-compile for a Cortex-M0+ target, and using the accompanying GDB to debug. I want to set a breakpoint on the following line of code: if (...
Jeremy's user avatar
  • 5,231
3 votes
0 answers
305 views

Cppcheck is returning different results on each scan

I'm trying to check embedded C code using Cppcheck (running on Windows 7, using GUI) but every time I click on "Reanalyze all files" I get different results. The code is meaned to get build ...
viper1209's user avatar
3 votes
3 answers
485 views

Code sharing between multiple independently compiled binaries/hex files

I'm looking for documentation/information on how to share information/code between multiple binaries compiled for a Cortex-m/0/4/7 architectures. The two binaries will be on the same chip and same ...
Siho's user avatar
  • 130
3 votes
0 answers
799 views

How do you clear the branch predictor cache in a cortex-m7?

BPIALL is documented as not implemented, but the branch predictor is documented and easy to see in testing that it is implemented. The BTAC bits in the ACTLR work as described, you can basically ...
old_timer's user avatar
  • 70.7k
3 votes
1 answer
2k views

Cortex M0+ (SAMD21) not executing pending interrupt

I discovered this issue when I tried to put the microcontroller to sleep and then wake it up, as an interrupt driven application. I noticed that my code did not resume from the line of code that was ...
Lance Molyneaux's user avatar
3 votes
0 answers
3k views

Documentation for LLVM ARM Assembler Directives

At the moment I'm looking at assembler code for the ARM Cortex-M3 generated by LLVM. LLVM generates a lot of assembler directives. As you can see in the example below: .text .syntax unified ...
konze's user avatar
  • 873
3 votes
1 answer
295 views

kill function from ISR on cortex-m0

I am using a Cortex-M0 processor with a bare metal implementation (no OS). We have a firmware application where we want to allow a third party to write a C function that will be built separate from ...
jdbk's user avatar
  • 41
3 votes
2 answers
277 views

malloc crashes embedded system

I am trying to multiply matrices of arbitrary sizes on a cortex M4-core. I DO need a malloc... But I don't understand why at the first call it works and at the second call it doesnt work any more. it ...
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