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AlaBek's user avatar
AlaBek's user avatar
AlaBek
HW Design Engineer
  • Member for 5 years, 11 months
  • Last seen this week
  • Oulu, Finland
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6
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3
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1
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1
Posts
11
Posts %
1
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1
Posts
11
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1
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1
Posts
11
Posts %
0
Score
3
Posts
33
Posts %
0
Score
2
Posts
22
Posts %
-1
Score
4
Posts
44
Posts %
Top posts
1
Parameter Overriding
Jul 5
0
Separating System Verilog nets before applying force
Jul 23, 2021
0
Is there a way in Systemerilog to know if data type is object type or other basic type?
May 12
0
Creating an array at specific address with predefined size
May 15
0
Testbench issue for glowing/fading LED not producing a waveform
Sep 8, 2023
0
Why does the s2 signal have the opposite value as the s3 signal after the nanosecond 20?
May 16
-1
Assign a Output into Two Modules in Verilog
Sep 12, 2023
-1
Questasim tool showing error after updating code and re running for schematic
Dec 11, 2023
-1
Verilog always @(posedge clk) dosent work
Jun 19