All Questions
30
questions
2
votes
1
answer
286
views
Headless build using Eclipse CDT with the IAR plugin
I have a C project which was created with Renesas e2studio for Synergy and compiled with IAR Embedded Workbench for Renesas Synergy.
I would like to take advantage of Eclipse's headless build option ...
- 560
0
votes
1
answer
316
views
Why I got this "Error[Ta087]: Register r8 not available to clobber in selected core/mode" on IAR EWARM
I am trying to compile an IAR project with mixed C and ASM for Cortex-M0, and I got an error of
Error[Ta087]: Register r8 not available to clobber in selected
core/mode
when I have this line
: "...
- 23
0
votes
1
answer
700
views
IAR equivalent symbol to __bss_end__
I want to know where is the end of my static data in RAM of Cortex-M. GCC CMSIS linker scripts provide a symbol for __bss_end__ and I simply take its address. Is there an IAR equivalent? Or do I have ...
- 251
1
vote
1
answer
216
views
How do I find undefined functions and add/link them as external functions?
I'm new to IAR workbenches in general (and EWARM to be precise), so I have a couple of potentially silly questions.
For starters, here's what I actually want to do and the questions aroused:
I need ...
- 195
1
vote
1
answer
8k
views
How can I solve "Linker Section Placement Error" in IAR
I am trying to run some basic Ethernet applications (via lwIP) on an ARM Cortex M3 which is on board a M2S150 Development kit and have run into an issue I don't understand:
Error[Lp011]: section ...
4
votes
1
answer
1k
views
Code Size Comparison Cortex M3: IAR ARM vs Keil µVision
I am currently developing a small project for an STM32F103 microcontroller which features a Cortex-M3 CPU.
Due to CMSIS standard header files it is possible to use the exact same code with IAR and ...
- 1,662
0
votes
1
answer
92
views
Hard fault in STM32F101RF due to MRC2 Disassembly?
I am having a bootloader code wherein I will sending/receiving data via USART . I have configured USART to operate in interrupt mode.
USART functionality works perfectly fine independently. Verified ...
- 41
0
votes
1
answer
2k
views
Is there a Simulator for IAR?
I'm searching for IAR Simulator where I can run my code without the hardware. If there is, is there a trail period? And also where can I download it and how do I simulate? The hardware I'm looking at ...
3
votes
1
answer
530
views
Why do I need to subtract 1 from label in LDR instruction?
I am working on an ARM Cortex-M4 processor using IAR Embedded Workbench. When the main stack overflows I get a bus fault. I have therefore written a small function in assembly to check if the bus ...
- 165
2
votes
2
answers
1k
views
Cortex M3 jump from application back to bootloader and back to application
I have a bootloader and a firmware where the initial jump from bootloader to firmware works like a charme but when I have the scenario jumping back from application, make some stuff and jump back to ...
- 23
2
votes
1
answer
305
views
How to check SRAM usage for cortex m3 for an application
For Cortex-M3, how to check maximum SRAM usage by an embedded application running on it. Should we check linker map file and stack usage generated by IAR or should we try with writing a function which ...
-1
votes
1
answer
2k
views
IAR compiler "stdio library"
I am using IAR embedded workbench software for ARM CORTEX M7 controller. I have already included stdio.h library and it have fopen function like this
but when i am declaring my file pointer like ...
- 43
1
vote
1
answer
1k
views
IAR Embedded Workbench for ARM 8.22.2 - No Register View anymore
Am I the only one who is missing the register-view in IAR Embedded Workbench for ARM Version 8.22.2 (the latest)?
As described here https://www.iar.com/support/resources/articles/debugging-with-...
- 1,662
-1
votes
2
answers
335
views
How to force IAR to use desired Cortex-M0+ instructions (optimization will be disabled for this func.)
I need to force IAR tp use certain Cortex-M0+ instruction in some part of my code while codding with C.
Please do not offer pure asm functions or inline asm etc.
I have managed to do this for 51 ...
0
votes
1
answer
332
views
does the Keil cortex-m C compiler always compile functions address 4-byte align?
I am trying to copy a function from FLASH to memory, if i use word copying it will be faster, but he STM and LDM instructions require the addresses are 4-byte aligned, so i wonder generally comtex-m C ...
- 366