Questions tagged [cortex-m]
For all ARM Cortex-M series cores, including M0, M0+, M1, M3, M4, M7, M23 and M33.
cortex-m
1,421
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Local variable allocation crashes the stack in embedded C on cortexm4 and operating system
Details: embedded C, cortex M4 with operating system (RTX Kernel), compiled with ARM Compiler V5.06 update6 and Microlib.
Inside a periodic task there are some functons call, one is a debug function:
/...
- 315
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50
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ARM Cortex M4 context switching: How does the hardware know where xPSR, PC, LR, R12, R3-R0 are on the stack?
I'm working on a context switching mechanism for my RTOS which runs on Cortex-Ms.
When I initialize a task's stack, I have it like this
Then, I decrement the stack pointer 8 times to fit R11-R4.
I ...
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1
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Is the libsnark library compatible with the arm-none-eabi toolchain for ARM Cortex-M microcontrollers?
I am currently working on a project that involves implementing cryptographic protocols on ARM Cortex-M microcontrollers, specifically the Raspberry Pi Pico (RP2040). I am interested in using the ...
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35
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Can i boot from sram when i use arm cortex m3
normally,we boot from flash or ROM, but what if i want to boot from SRAM area(0x20000000_0x3fffffff) instead of Code area(0x00000000_0x1fffffff), should i use startup.s to copy the code to SRAM area?
...
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47
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Unwinding Stack on Cortex-M with FreeRTOS: Handling Interrupts and Stopping Conditions
I am writing an unwinder for a Cortex-M (an ARM processor) running FreeRTOS. It mostly works, and I can trace the stack in many cases, but I have encountered a few issues that I haven't been able to ...
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1
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41
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Taking FreeRTOS as an example, how to separate the kernel from the application? (Physical)
enter image description hereBackground: FreeRTOS, Cortext-M3
Suppose there is a situation where the kernel and application are developed separately, and the .text segment of the kernel and the ...
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1
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52
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How/When exactly does Cortex-M4 (STM32 F4) switch its R13 from MSP to PSP? Do i have to manually switch if using PSP in inline asm?
I'm writing my own RTOS and I'm implementing the context switch function, where I have to use PSP. The function is written in inline assembly
I was working on another project on STM32 F4 writing ...
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3
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1
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53
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Missing ELF symbol for extern const float?
I have seen Missing ELF symbol "var" when using GDB? , but this is a different issue.
I am using gdb with RP2040 over openocd. Unfortunately I cannot provide a full code that reproduces the ...
- 5,129
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How to correctly implement delay after enabling RCC peripheral clock?
I'm new to STM32 microcontrollers. I would like to know how to correctly implement 2-clock-cycle delay after enabling RCC peripheral clock.
Section 5.2.16 (page# 134) of https://www.st.com/resource/en/...
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Embedded C++ - Header-only library optimization level
I mainly develop firmware for ARM Cortex M using gcc and I am migrating from C to C++ and even though I am overall happy with the transition, there are some things that I just can't get right.
...
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27
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Build valgrind to target LPC55S69(which is based on Armv8-m architecture)
I'm trying to build valgrind to target baremetal arm cortex-m (based on armv8-m architecture). The host is a x86 wsl environment. How do I specify this while trying to configure valgrind.
For ex: To ...
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1
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37
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ARM Cortex-M Trustzone (ab)use to isolate third party application
I am new to trustzone on the Cortex-M and am wondering if I can use it to isolate a third party application from a bunch of legacy code.
The idea would be to move the legacy code with freertos into ...
- 4,949
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VSCode Arduino environment, SAMD51J19A, persistent DummyHandlers
I've been developing an embedded application for months for an Adafruit Feather M4 Express board. I'm using the VSCode Arduino environment, and it's been going well, up until:
After putting down the ...
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How to determine if interrupts are enabled Arm Cortex M4F (STM32G44)
I have a function that is called when the interrupts are enable and other times when disabled and it must behave different depending on the interrupt enabled state.
I reviewed the reference manual but ...
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2
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47
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Can I service the SysTick interrupt while already in HSEM interrupt (STM32H745, M4 core)?
I have a situation where my software enters a HSEM interrupt (with the M4 core) and while it is servicing that interrupt it is ignoring the SysTick interrupt. Exiting the HSEM interrupt is dependent ...
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35
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Ho to use CMSIS-Core (Cortex-M) for TM4C123GH6PM and TM4C129ENCPDT in Code Composer Studio
I'm trying to write drivers for TM4C129ENCPDT and TM4C123GH6PM in Code Composer Studio(Linux). I prefer to use CMSIS and not Tivaware. I'm unable to get the CMSIS-Core Device Files (provided by ...
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15
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Can't find the 'No Access' permission in Cortex M55 MPU
I'm trying to configure the MPU region, but I can't find the 'No Access' permission.
There are only Read/Write permission.
How can I configure a memory region to 'No Access' in Cortex M55?
I read a ...
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1
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42
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Analyzing Relocations in ARM for cortex-m4
I'm trying to understand how to correctly read the relocation entries generated by my ARM compiler (I'm using (GNU Arm Embedded Toolchain 9-2020-q2-update) 9.3.1 20200408 (release)).
To my ...
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Position-Indipendent FW for Cortex M
Due to a educational requirement, I need to write a FW that can be run in RAM at non-predetermined locations.
First of all I don't know which gcc parameters are needed, although I think it's either -...
- 1,408
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How TBB and DCB work in branching the flow?
I am new to ARM Cortex and facing difficulty to understand how TBB branches.
Code snippet attached:
TBB [PC,R1]
BrTable1
DCB ((P0 - BrTable1)/2)
DCB ((P1 - BrTable1)/2)
Now, my understanding is as ...
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1
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64
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ARM GCC fails to create a working binary for STM32F4, lot of discarded code
I've been migrating all my STM32 projects to Codeblocks IDE and GCC compiler (arm-none-eabi).
The process is using STM's CubeMX to generate the base code, then merge everything to a proper folder with ...
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1
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34
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MPU protected region not protected against EEFC_FCR ES erasure (cortex m4)
I set up an MPU region on a Cortex-M4 with AP encoding 000 (no access),
MPU->RBAR = address | (1 << 4) | (1 << 0);
MPU->RASR = (1 << 17) | (1 << 3) | (1 << 0);
MPU-&...
- 73
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92
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Detect if running inside QEMU
I'm working on some bare metal Cortex-M4 code. It usually runs on a dev board, but to run unit tests I emulate it under QEMU. However, some hardware configurations are done differently depending on ...
- 2,684
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48
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MCU SysTick infinite loop
During the development of an embedded device, I encountered a one time bug with no interruptions working. It's important to understand that this device usually works fine, and has been for a few years ...
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1
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1
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171
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ARM Cortex-M PC and SP values - reset behavior
I am trying to understand the ARM cortex-M hardware behavior on reset; particularly how the SP and PC values are written upon a cold start or hard reset.
Basically, it would seem the hardware (aka PE ...
- 11
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15
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When debugging with J-link, where is the program executed?
I used the SDK provided by DesignStart to build a minimal system based on Cortex M3 in Verilog language, using an SRAM module to connect I-code, D-code to act as on-chip Flash, and another SRAM module ...
- 105
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3
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167
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How to perform a MCU reset after a specific hardfault?
As I didn't find an existing questions on stackoverflow or on google, please find the context below.
I'm investigating an issue leading to 2 different hardfaults on ARM Cortex-M33.
The first one ...
- 520
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47
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Is there a way to add Local Symbol names in the ELF file by adding debug flags to the arm-none-eabi-gcc compiler?
I am able to view the global symbols such as functions, global/static variables in the final built executable in elf file. I am looking for compilation flags that can add the local variable names into ...
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42
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STM32 stall after implementing STOP2 mode. Implementation of a interrupt based keyboard in Nucleo-L412KB
I have implemented a serial keyboard with a Nucleo-L412KB board (bare-metal). The switches are arranged in nine rows (output pins driven high) and seven cols (input pins pulled-down, with interrupts ...
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47
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Why veneer code generated by gcc for cortex-m0 seems 8-byte aligned?
The interesting observation I made recently while using GCC to compile for a Cortex M0 is that the veneer code generated in my project appears to be aligned to 8-byte boundaries.
Slightly modify the ...
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