Questions tagged [cortex-m]
For all ARM Cortex-M series cores, including M0, M0+, M1, M3, M4, M7, M23 and M33.
cortex-m
1,421
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Ho to use CMSIS-Core (Cortex-M) for TM4C123GH6PM and TM4C129ENCPDT in Code Composer Studio
I'm trying to write drivers for TM4C129ENCPDT and TM4C123GH6PM in Code Composer Studio(Linux). I prefer to use CMSIS and not Tivaware. I'm unable to get the CMSIS-Core Device Files (provided by ...
- 9
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15
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Can't find the 'No Access' permission in Cortex M55 MPU
I'm trying to configure the MPU region, but I can't find the 'No Access' permission.
There are only Read/Write permission.
How can I configure a memory region to 'No Access' in Cortex M55?
I read a ...
- 1
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1
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42
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Analyzing Relocations in ARM for cortex-m4
I'm trying to understand how to correctly read the relocation entries generated by my ARM compiler (I'm using (GNU Arm Embedded Toolchain 9-2020-q2-update) 9.3.1 20200408 (release)).
To my ...
- 3
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Position-Indipendent FW for Cortex M
Due to a educational requirement, I need to write a FW that can be run in RAM at non-predetermined locations.
First of all I don't know which gcc parameters are needed, although I think it's either -...
- 1,408
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How TBB and DCB work in branching the flow?
I am new to ARM Cortex and facing difficulty to understand how TBB branches.
Code snippet attached:
TBB [PC,R1]
BrTable1
DCB ((P0 - BrTable1)/2)
DCB ((P1 - BrTable1)/2)
Now, my understanding is as ...
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1
answer
63
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ARM GCC fails to create a working binary for STM32F4, lot of discarded code
I've been migrating all my STM32 projects to Codeblocks IDE and GCC compiler (arm-none-eabi).
The process is using STM's CubeMX to generate the base code, then merge everything to a proper folder with ...
- 11
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1
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34
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MPU protected region not protected against EEFC_FCR ES erasure (cortex m4)
I set up an MPU region on a Cortex-M4 with AP encoding 000 (no access),
MPU->RBAR = address | (1 << 4) | (1 << 0);
MPU->RASR = (1 << 17) | (1 << 3) | (1 << 0);
MPU-&...
- 73
1
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1
answer
92
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Detect if running inside QEMU
I'm working on some bare metal Cortex-M4 code. It usually runs on a dev board, but to run unit tests I emulate it under QEMU. However, some hardware configurations are done differently depending on ...
- 2,684
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48
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MCU SysTick infinite loop
During the development of an embedded device, I encountered a one time bug with no interruptions working. It's important to understand that this device usually works fine, and has been for a few years ...
- 43
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171
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ARM Cortex-M PC and SP values - reset behavior
I am trying to understand the ARM cortex-M hardware behavior on reset; particularly how the SP and PC values are written upon a cold start or hard reset.
Basically, it would seem the hardware (aka PE ...
- 11
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15
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When debugging with J-link, where is the program executed?
I used the SDK provided by DesignStart to build a minimal system based on Cortex M3 in Verilog language, using an SRAM module to connect I-code, D-code to act as on-chip Flash, and another SRAM module ...
- 105
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3
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167
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How to perform a MCU reset after a specific hardfault?
As I didn't find an existing questions on stackoverflow or on google, please find the context below.
I'm investigating an issue leading to 2 different hardfaults on ARM Cortex-M33.
The first one ...
- 520
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47
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Is there a way to add Local Symbol names in the ELF file by adding debug flags to the arm-none-eabi-gcc compiler?
I am able to view the global symbols such as functions, global/static variables in the final built executable in elf file. I am looking for compilation flags that can add the local variable names into ...
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42
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STM32 stall after implementing STOP2 mode. Implementation of a interrupt based keyboard in Nucleo-L412KB
I have implemented a serial keyboard with a Nucleo-L412KB board (bare-metal). The switches are arranged in nine rows (output pins driven high) and seven cols (input pins pulled-down, with interrupts ...
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Why veneer code generated by gcc for cortex-m0 seems 8-byte aligned?
The interesting observation I made recently while using GCC to compile for a Cortex M0 is that the veneer code generated in my project appears to be aligned to 8-byte boundaries.
Slightly modify the ...
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