Questions tagged [cortex-m]
For all ARM Cortex-M series cores, including M0, M0+, M1, M3, M4, M7, M23 and M33.
cortex-m
1,422
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writing and reading from the same memory address from two different QEMU instances
I have a code to write "Hello" at the memory address 0x10000000, and another code to read the value from this memory address and print it out. I have defined 0x10000000 as a shared memory in ...
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1
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2
answers
746
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Debug not working with Cortex-Debug on relocated application on STM32
I'm working on STM32F407 device, developing a Bootloader and Application
The environnement is Visual Studio Code, and using Cortex-Debug extension for the debug.
The bootloader at address 0x0800 0000 ...
- 11
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1
answer
51
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Why sub instruction modifies the xpsr register and puts a carry flag for 9-7
I'm using STM32cubeIDE and debugging assembly on a cortex m4. I meet a strange behaviour when trying the instruction SUB. according to documentation,the SUB instruction shouldn't change the XPSR ...
- 21
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135
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qemu: fatal: Lockup: can't escalate 3 to HardFault (current priority -1)
I have encountered this error while working with QEMU, specifically a Hardfault error when emulating the MPS2AN505 with a Cortex-M33 core. The error I am facing is as follows:
qemu: fatal: Lockup: can'...
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1
vote
1
answer
98
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Mysterious ARM Opcode
In decompiling a hex file for a Texas Instruments ARM (Thumb 2) Cortex-M4f processor (CC2652RB), I have come across an opcode that I can't figure out.
What does "90 FF FF 00" do (maybe the ...
- 297
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1
answer
105
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Cortex M7 abnormal instruction-fetch behavior
I am a MCU digital IC designer. In our MCU design, we used Cortex-M7 to control our system. A random problem occurs during my simulation.
The LD file defined the RAM/CODE region(0x2801000~0x28030000), ...
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votes
1
answer
689
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Heap and Stack allocation in ThreadX RTOS
Recently I started learning ThreadX RTOS and I noticed that in the linker script and crt0.S provided for Cortex-M4 with gcc toolchain, .stack and .heap sections are allocated with size 1024 bytes and ...
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1
answer
356
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vscode cortex-debug halt stm32
Hi i wanted to know if there was anyway to stop the program halting when i attach to stm32
launch.json
{
"name": "Attach STM32 STLink",
"showDevDebugOutput": "...
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votes
0
answers
56
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i.MX8MP: Which .dts file addresses are accessible to both processors at once?
Which of these memory areas can be used simultaneously by two cores - Cortex M7 and Cortex A53? And how can I do this? What address do I need to specify for the mmap function on the Linux side so that ...
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35
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unprivileged to privileged in Thread mode
can switching from unprivileged to privileged mode be done without having to switch from thread mode to handler mode or can i just switch to privileged mode without necessarely switching to handler ...
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votes
1
answer
118
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Cortex M4 stacking and unstacking with a diferent stack pointer
It is possible to achieve this in a cortex-m4? What i mean is having PSP only on that intervals, and all the rest MSP when there is an interrupt?
The objective is just to do the stacking and ...
- 3
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1
answer
183
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How is this ARM (Thumb) LDR Instruction being calculated?
The code is running on a Cortex M0+. I am trying to calculate the addresses of LDR PC-related loads and am finding the addresses are not always consistent.
This LDR PC-related load does not follow ...
- 531
1
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0
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152
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Baremetal Cortex-M7 gcc and unwind tables without libunwind
I'm working on a project using an STM32H743 MCU which has a Cortex-M7. I'm building outside of ST's toolchain and IDE with gcc-arm-none-eabi (13.2 Rel 1). My project is written entirely in C and ...
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1
answer
129
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Can somebody translate this ASM instruction code for Cortex M7?
" mrs %0, ipsr " : "=r" (reg_tmp)
I need to translate this ASM code out-of-curiosity, it is for ARMV7 specifically cortex-M7 executing in privileged mode. I know MRS instruction ...
- 55
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1
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177
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Arm cortex m0 LDR instruction
What is the difference between these instructions in the ARM Cortex M0?
LDR r1, r2
LDR r1, [r2]
MOV r1, r2
Is any of them wrong?
If none of them is wrong, why would I use the second one to load from ...
