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1 vote
1 answer
58 views

gnu inline assembly constraint `i` for memory address

Recetly, this function rip_rel_ptr has been added to Linux kernel. https://elixir.bootlin.com/linux/latest/source/arch/x86/include/asm/asm.h#L118. I can compile the kernel, but when I copy this ...
amrzar's user avatar
  • 367
8 votes
1 answer
230 views

Purpose of '*&x' in inline assembly?

Looking at some x86_64 GCC inline assembly, I have come across the following construct: int x; __asm__( "<opcode> %0" : "=m" (*&x) ); ^^^ ...
DevSolar's user avatar
  • 69.5k
2 votes
1 answer
107 views

What does `+&` mean in gcc inline assembly?

I'm aware that when using gcc inline assembly, if you don't specify otherwise, it assumes that you consume all your inputs before you write any ouput operand. If you actually want to write to an ...
ChristmasTree's user avatar
1 vote
1 answer
116 views

Using FSIN through inline-assembly

I want to use x87's FSIN through gcc's / clang's inline assembly. How would a sin()-function using an __asm__-block internally for that look like with a 64 bit double parameter ? Using __builtin_sin() ...
Edison von Myosotis's user avatar
0 votes
0 answers
43 views

the difference between two style of inline ASM

My code print FAIL as follow: Need someone to explain the difference. I want to know the difference between __asm__ __volatile__( "addl %1,%0;" :"=r"(sum) :"r"...
Young Warrixy's user avatar
0 votes
1 answer
53 views

How can I create an Inline assembly command with a multi-variable register offset?

The following code, using gcc for ARMv4, is perfectly fine: asm("strb.w r2, [r0, #24 + 8 * 1]"); Now, if I try the following: asm("strb.w r2, [r0, %[offset] + %[delta] * %[scale]]"...
Hansel's user avatar
  • 257
0 votes
0 answers
48 views

gcc inline assembly fails for compiler option -O2 [duplicate]

When the compiler optimize option -O2 is set, the output is empty dst: However, if -O2 is removed, the output appears dst: 123456789 Why does adding -O2 cause nothing to display (-O1 works fine)? ...
vengy's user avatar
  • 2,125
0 votes
1 answer
162 views

Why is this inline ASM function adding the first input operand twice? [duplicate]

I'm a beginner to assembly and a novice programmer in general. I'm trying to wrap my head around the basics of assembly by writing some basic inline asm functions in C++. I'm compiling with GNU g++, ...
MAA1117's user avatar
2 votes
0 answers
253 views

How to write _start function to call the main function in C

By using inline assembly asm volatile, how can I implement _start function in C which can call the main function int main(int argc, char *argv[], char *envp[]) I tried alot, but it didn't work at all,...
Muhab Joumaa's user avatar
1 vote
1 answer
88 views

Cannot specify the operands when using inline asm outside a function

My code is unsigned long user_stack_pointer; __asm__( ".global exception_handling_entry\n" "exception_handling_entry:\n" "add %0, sp, x0\n" : "=r&...
maplgebra's user avatar
  • 123
0 votes
0 answers
52 views

What do the numbers in "%0" or "%1" mean in C/C++ GCC Inline Assembly [duplicate]

I'm Reading the gcc documentation about the inline assembly,there was an operand syntax like %0,%1,%2 what this number mean ?, in their documentation this is not explained.
Darevil294's user avatar
0 votes
0 answers
48 views

Why is RISC-V GCC breaking my code when optimizations are enabled? [duplicate]

I have the following C code for 32-bit RISC-V: static void test(uint32_t key, uint32_t chr, uint32_t state) { char s[2]; if(state != KEYSTATE_PRESSED) { return; } if(!isprint(chr)) { ...
anton-tchekov's user avatar
0 votes
1 answer
59 views

gcc inline asm / constraints / "r" relates to "l" like "g" to ...?

I'm trying to compile this for an ARM Cortex-M0+ (STM32G030) with arm-none-eabi-gcc: asm("ldrb %0, [%1, %2]\n" : "=l" (v) : "l" (R.a+(o&~31)) , "g" (o&...
RRIDDICC's user avatar
  • 119
3 votes
1 answer
337 views

RISC-V GCC Compiler compiles ASM code incorrectly

I am writing an embedded C program to test a hardware IP that I have developed on an FPGA board. I was playing with the RISC-V GCC ASM syntax and found this weird issue. This is the code that I ...
Mohammed Arshaan's user avatar
0 votes
0 answers
171 views

RISCV64 `li` pseudo instruction and inline asm operand constraints

I work on bare-metal with C99. Please consider... #define FOO 0x234567894567ULL extern void someFunction(void); void example(void) __attribute__((naked)); void example(void) { __asm__ volatile( ...
Lance E.T. Compte's user avatar

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