Questions tagged [cpu-architecture]
The hardware microarchitecture (x86, x86_64, ARM, ...) of a CPU or microcontroller. Use this tag for questions regarding features, bugs and details concerning the inner working of specific CPU architectures.
cpu-architecture
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MESI: why we need write-miss to move from shared to modified
The book "Computer Architecture", by Hennessy/Patterson, 6th ed, on page 394, includes an example with true sharing and false sharing misses with 2 processors.
here is the example from the ...
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Are the Retirement unit/Reorder Buffer (ROB) one for the whole processor or one per core?
Is there one Retirement unit/Reorder Buffer (ROB) per core or one for the whole processor? Also, is there one retirement unit per core or one for the whole processor?
To be honest, I'm not even sure ...
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Relationship between memory acceses and instructions in MIPS architecture
I'm currently studying computer architecture, following the Hennessy-Patterson books (Quantitative Approach 5 and Organizazion and Design 4), and I want to check if I'm understanding some cache ...
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Can a specialized assembly instruction be designed to shift memory block and simplify array insertion and deletion?
While learning about array operations, I've found that insertion and deletion can be cumbersome, requiring shifting elements one by one. Could we design a specialized assembly instruction that shifts ...
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Cause of 'Assertion `_numOutstandingPackets == 0' failed' in Gem5
I'm writing a new memory dependence predictor for the Gem5 O3 CPU. Currently the memory dependencies it sets is somehow causing a load instruction to fail this assertion when it's packets are sent to ...
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Is is possible to Connect one Master port to multiple Slave ports in GEM5?
I am trying to connect a master port of a ram to slave ports of multiple rams in my Python config file:
system.lvsram0.m0_port.connect(system.lvsram0.s0_ports[0])
system.lvsram0.m0_port.connect(system....
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Can you have multiple copies of same data in cpu cache
From wikipedia https://en.wikipedia.org/wiki/Cache_coherence
Multiple copies of same data can exist in different cache simultaneously and if processors are allowed to update their own copies freely, ...
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Can false sharing happen in Direct-Mapped Cache?
If each address in memory is directly mapped to deterministic location in cache, cache coherence is not needed because all thread that access share data share the same cache.
Ie. Within the context of ...
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At what point in the interrupt-processing path does device-driver code execute?
I am new to interrupt handlers and device i/o and I have a few questions:
When you load a device-driver, i.e. kernel module, its assembly code is stored in the module-mapping region of the Kernel ...
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While running a piece of driver code on an AMD64 machine, it appears that there are issues related to cache consistency or out-of-order execution
While running a piece of driver code on an AMD64 machine, it appears that there are issues related to cache consistency or out-of-order execution. Are there any experienced engineers who can help ...
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the Perf event issues of hardware prefetcher (all_pf_data_rd and pf_l2_data_rd)
My platform is 2nd generation scalable Xeon, equipped with a non-inclusive cache. I run a series of tests that had the L2 stream prefetcher aggressively prefetching.
I use Perf to monitor performance, ...
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How does one Compute Fractional Values into Different BCD Codes?
I know the basics of the Gray and 84-2-1 code, for example a value like 5 should be 1011 in 84-2-1
8 4 -2 -1
1 0 1 1
8 - 2 - 1 = 5
whereas in Gray Code it should be 101
101 (binary of 5)
add 1 to MSB ...
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comparing the performance of a x86 processor with gem5
I'm trying to create a gem5 implementation that is close to a x86 processor in terms of performance. However, I'm not sure which statistic I can use to compare the performance of the two.
I was ...
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lmc program division assembly languange
I'm trying to solve this challenge:
create a simple LMC program to determine if a number evenly divides another one:
Input 2 numbers
If they do not evenly divide, then the program outputs 0 and asks ...
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what openOCD does to spike while debugging a program with spike?
My initial aim is to understand how debug mode works to design the debug mode of a CPU. I am following the guidelines of the riscv-isa-sim repo to debug a program. The only difference is creating a ...
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