The schematic does not explicitly specify the potential of the lower node, and you are correct to question this. You are also probably correct that the author intended this to be 0V.
For the PNP transistor to stay in the active region (which I guess we want?)
No, we need the transistor to be saturated, or cut-off. That's because we require either 0V across the load, or the full 12V. In active mode, collector potential will be somewhere between the extremes of 0V and +12V, which is not the required behaviour. I can assume this, because control is via a switch, and not some arbitrary analogue signal, implying full on/off behaviour.
You are not told (in the snippet you provided) what the current gain \$\beta\$ of the transistor is. Maybe it's written elsewhere. Without that information, you can't know what base current is required to obtain the requisite amount of collector current.
I'll assume \$\beta=100\$.
You know the two required conditions of the transistor, fully off (cut-off) and fully on (saturated). In cut-off, collector current \$I_C=0\$, and the load will have 0V across it. For that condition, base current must also be \$I_B=0\$, which occurs when switch S is open. No further analysis required.
When the transistor is saturated, \$V_{CE}\$, the difference in potential between collector and emitter, is close to zero. I say close, because that's never true, \$V_{CE}\$ will more likely be 0.2V or so, or even more depending on the model.
Just for pedantry, being PNP, this transistor's datasheet will show a negative value for the parameter \$V_{CE}\$. Technically:
$$ V_{CE} = V_C - V_E $$
Since for a PNP transistor in normal use \$V_E\$ is always more positive than \$V_C\$, this will yield a negative value, but in a simple circuit like this, it's easier to say that in saturation, since the supply is 12V, and the transistor takes 0.2V of that, the load must have the remaining 11.8V across it.
It's not clear whether the question expects you to consider a non-zero \$V_{CE}\$ in your answer, but I'm going to ignore it here, and assume \$V_{CE}=0\$, and the full 12V appears across the load. This reveals collector current:
$$ I_C = \frac{12V}{5\Omega} = 2.4A $$
Then we can find the corresponding base current:
$$ I_B = \frac{I_C}{\beta} = \frac{2.4A}{100} = 24mA $$
As you correctly pointed out, the base-emitter junction of the transistor will develop about 0.7V. Strictly speaking \$V_{BE}=V_B-V_E=(+11.3)-(+12)=-0.7V\$, but again at a glance, we know that the remaining 11.3V must exist across \$R_A\$. Knowing the required base current \$I_B=24mA\$:
$$ R_A = \frac{11.3V}{24mA} = 470\Omega $$
If \$R_A\$ were larger than that, base current would fall to a level insufficient to saturate the transistor. With a smaller \$R_A\$, base current would increase, and the transistor would remain saturated.
Therefore this value for \$R_A\$ is a maximum.
In real life, there are some caveats to consider. It's common practice to aim for a base current at least twice the calculated value (\$R_A=\frac{11.3V}{48mA}=240\Omega\$), or up to ten times that (depending on the application and the load) for a couple of reasons:
\$\beta\$ is very approximate. It could be significantly lower or higher, varying from transistor to transistor, so you must design for worst-case conditions. Perhaps you'll get unlucky and find a device with \$\beta=50\$.
\$\beta\$ drops off dramatically as the transistor approaches saturation.
Since in practice we aim for base current significantly higher than the theoretical minimum for saturation, the small inconvenience \$V_{CE}\ne 0\$ is really insignificant.