Is there any way to explicitly tell compiler to stop optimization

Question

Linux, C, GCC, ARM (Allwinner H3). Is it possible to get the following equivalent functionality (pseudocode):

#pragma optimizations-stop
#pragma registers-flush

a=10;
while(*b != 0) c++;
if(a == 0) { do something; }

#pragma optimizations-start

with result of location of a being explicitly written with value 10, then every loop cycle value of b is read from the memory and then read value from location b is compared to 0, and then if not zero c is rmw'ed with +1, and when loop breaks location of a is being explicitly read from the memory and compared to 0?

And, what's important, instructions are executed in the specific order programmer laid them out in the program, not as compiler or CPU thinks the best.

Please withhold with discussion of what is impossible, let's discuss how to achieve the required result.

If it is not possible at the C/GCC level, I will be glad for suggestions to implement that as inline assembly.

Answer 1

The "big hammer" is a GCC extension, asm __volatile__("": : :"memory"). This is the full memory barrier used by the Linux kernel.

Note that this does not do what you ask for in the title. It doesn't stop optimizations at all. It does however achieve the ordering that you describe.

Also note that c++ is a read-modify-write. It's not atomic, and there are no memory barriers between the parts. The compiler can reasonably keep c in a register, and do a read-modify-write on the register. You'd need something like volatile int* pc = &c; to avoid that.

Finally, to take your other post into account, the memory barrier on one thread won't magically make another thread cooperate. You'd need barriers on both threads. And that's why they're rare - you can usually use proper synchronization instead.

Answer 2

Using _Atomic for all the variables in question will achieve this:

1. Every read and write to an _Atomic variable will correspond to an actual load or store instruction being executed. (While this is not a formal guarantee of the C standard, in practice compilers do not try to optimize them out.)

2. Those loads and stores will not be reordered by the compiler.

3. Memory barrier instructions will be inserted where needed, to prevent any reordering by the CPU and ensure that they are observed in the same order by every other thread / CPU which also uses proper barriers. (The default memory ordering for atomic is sequential consistency. To avoid any of these memory barriers, you'd need to use functions like atomic_load_explicit).

4. The c++ will be performed with an atomic read-modify-write instruction or sequence of instructions (e.g. ARM LDREX/STREX), so that no writes to c can be performed by any other thread in between the read and write.

5. Accesses to non-_Atomic variables will not be reordered after a store, nor before a load. (You can't prevent reorderings in the other directions, except by making the other variables _Atomic as well.)

Note that using volatile, as suggested elsewhere, achieves 1 and 2, but typically not 3, 4, 5. Moreover, any unsynchronized concurrent access by multiple threads to a variable which is not _Atomic, even if it is volatile, causes undefined behavior for the entire program according to the C standard (a data race).