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Verilog primer

Verilog primer - FPGA Tutorial

From the course: Learning FPGA Development

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Verilog primer

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- In most of the next videos I'll show you some examples in Verilog, so here's a quick description of the basic elements of this language for you to get familiar with it. We'll quickly talk about modules, declarations, primitives, concurrent elements, and control statements. As we saw earlier, a module declaration consists of the module keyword followed by the name of the module and a port list. Here we have a four bit adder, which takes as input a four bit number A, a four bit number B, which are the addition upper ends, and then its outputs are a four bit number S, which contains the results of the addition, and one bit number Co, which is the carry output bit. Notice that both outputs are defined as registers with the reg keyword. Registers in Verilog are data storage units, so they can hold a value assigned to them. The definition of a module is terminated with the endmodule keyword. Let's take a look at some examples of declaration in Verilog. There are two types of signal…

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