From the course: Learning FPGA Development

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Verilog and VHDL

Verilog and VHDL - FPGA Tutorial

From the course: Learning FPGA Development

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Verilog and VHDL

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- [Instructor] Now let's see what hardware description languages, or HDLs, are. First, the purpose of an HDL is hardware entry for your toolchain to understand what system you want to produce. A simulator may be used to interpret your code in order to predict its behavior. And later a synthesis tool may be used to implement the design in a field programmable gate array or in an application specific integrated circuit. The built in structure of an HDL based project consists of two categories of modules. Descriptive modules, where you define your hardware and test bench or stimulus modules, where you enter a sequence of inputs to your system. Test bench modules are used by simulators to execute the steps you entered and produce the results you want to see. Here we have two code examples for the same module in Verilog and VHDL. The module is the one shown in the schematic diagram and it's a halfAdder, a basic block to implement a circuit that adds two integers. A halfAdder calculates the…

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