Suhail Hasan

We encourage you to read the recently published article "Design of Broadband Doherty Power Amplifier Based on Single Loop Load Modulation Network". Authored by: Ge Bai; Zhijiang Dai; Jingsong Wang; Cheng Bi; Weimin Shi; Jingzhou Pang; Mingyu Li 📝 Volume: Volume: 14, Issue: 1, March 2024 For future sixth-generation wireless communications (6G), it is urgent to explore new power amplifiers (PAs) architectures with high efficiency, large bandwidth, and large back-off. Doherty power amplifier (DPA) requires an impedance inverter network (IMN) to achieve load modulation, which limits the operating bandwidth of the DPA. This paper presents a novel DPA architecture with broadband and high efficiency, referred to as single-loop load matching network DPA (SL-LMN). 🔗 Continue reading on IEEE Xplore here: https://loom.ly/pjASqjM #JETCAS #CircuitsandSystems #graphicalabstract #ReadMore

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#HBM4 set to land sooner than expected 💡 Suppliers and JEDEC are bringing their HBM4 plans forward as they suspect the forecasted Gen #AI boom means incoming NVIDIA GPUs will need it sooner. High bandwidth memory (#HBM) bypasses #X86 socket-connected #DRAM capacity and bandwidth limits by having #memory dies stacked on top of a logic layer, with interconnecting TSV channels, all linked to a #GPU via an interposer component providing higher bandwidth than X86 sockets. The Joint Electron Device Engineering Council (JEDEC) confirms and issues HBM standards, with the current one being its fifth, HBM3E (extended). JEDEC has said it will issue a completed HBM4 spec by the end of this year – just few months ago the schedule was for a 2025 delivery. Preliminary HBM4 characteristics are emerging already. Thanks again to Chris Mellor and Blocks and Files for the full article with more background and insights via the link below 💡🙏👇 https://lnkd.in/eZp_wyHB #semiconductorindustry #semiconductors #semiconductor #technology #tech #innovation #semiconductormanufacturing #it #chip #chips #ic #it

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#TMS320VC5502PGF300 The TMS320VC5502 (5502) fixed-point digital signal processor (DSP) is based on the TMS320C55xTM DSP generation CPU processor core. The C55xTM DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform data transfers independent of the CPU activity. The C55xTM CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit × 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU. The C55x DSP generation supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions. The 5502 peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM and synchronous burst RAM. Additional peripherals include UART, watchdog timer, and an I-Cache. Three full-duplex multichannel buffered serial ports (McBSPs) provide glueless interface to a variety of industry-standard serial devices, and multichannel communication with up to 128 separately enabled channels. The host-port interface (HPI) is a 8-/16-bit parallel interface used to provide host processor access to 32K words of internal memory on the 5502. The HPI can be configured in either multiplexed or non-multiplexed mode to provide glueless interface to a wide variety of host processors. The DMA controller provides data movement for six independent channel contexts without CPU intervention. • High-Performance, Low-Power, Fixed-Point TMS320C55xTM Digital Signal Processor (DSP) – 3.33-/5-ns Instruction Cycle Time – 300-/200-MHz Clock Rate – 16K-Byte Instruction Cache (I-Cache) – One/Two Instructions Executed per Cycle – Dual Multipliers [Up to 600 Million Multiply-Accumulates Per Second (MMACS)] – Two Arithmetic/Logic Units (ALUs) – One Program Bus, Three Internal Data/Operand Read Buses, and Two Internal Data/Operand Write Buses

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More about DSP: DSP can be designed using dedicated hardware or processors or DSP processors. Floating point DSP and fixed point DSPs are common implementation types. Main applications are: audio signal processing(RF2bits), broadband communication, speech processing, data compression for storage, equalization, noise cancellation, automotives, #robotics, digital communication(set-top box, antennae etc) , #wireless #communication, streaming data, static data, #image-processing, #AI, #RADAR for military, medical field etc. DSP processors could be different from general purpose processors in terms of pipelining, Multiplier Accumulator(MAC) instructions, data bus etc. Area and power can increase significantly while designing DSP #hardware, one needs to be very careful. This is because it is #datapath intensive, as it has multipliers and accumulators all across. Some of the maximum speeds of the available #DSP processors is, around 2400 Million floating operation per second. DSP increases the throughput by opting for various techniques in parallel processing and pipelining. DSP techniques are used for real time #filtering and #decimation of radar signals to improve signal to noise ratio and processing efficiency. Digital signal processors (DSPs) can also be used to provide gradient processor control for properly manipulating MRI system magnets. DSPs are also useful for implementing signal processing functionalities in MRI devices. MRI reconstruction is based mostly on 2-D fourier transformation.

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We all consider the first-time silicon success, and it matters. An article "Trouble Ahead For IC Verification" on SemiEngineering discusses the increasing challenges in integrated circuit (IC) verification, highlighting both technical and human factors contributing to the decline in first-time silicon success rates. https://lnkd.in/gpdrEUQi Key Issues Identified: 1. Verification Complexity: Verification complexity is rising exponentially with design complexity. Advanced technologies and new application areas (e.g., automotive) introduce new verification challenges like thermal issues and parametric variations. 2. Human Factors: Major contributors to verification issues include schedule pressures, specification changes, and human errors. 3. Safety and Security Requirements: Advanced technologies like 2.5D/3D-IC and new application areas such as automotive and IoT introduce new, stringent safety and security requirements. 4. Process Immaturity: Many companies, especially new entrants, lack mature verification processes. By addressing these issues through improved tooling, better management of human resources, and adapting to new technological requirements, the IC verification process can be made more robust, ultimately improving first-time silicon success rates. In addition, I think we may considering to enhance collaboration with foundries. - Early Engagement: Engage with foundries early in the design process to ensure alignment on process technologies, design rules, and verification methodologies. - Design Rule Checks (DRCs) and Layout Versus Schematic (LVS): Collaborate closely with foundries to ensure that DRCs and LVS checks are integrated into the verification flow, reducing the likelihood of silicon respins. - Process Design Kits (PDKs): Utilize the latest PDKs provided by foundries, which include detailed information on process variations, to enhance the accuracy of simulations and verification. - Joint Development Programs: Participate in joint development programs with foundries to co-develop verification methodologies tailored to specific process technologies.

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When RAN engineers employ AI/ML to address system problems, they often become fixated on a single AI/ML model selection. However, solving complex RAN system issues necessitates the flexibility to utilize multiple AI/ML models including GenAI. Here’s a typical example. ◼ The Cell Edge Performance Problem in 5G RAN The cell edge problem refers to the degraded performance experienced by user equipment (UE) located at the boundaries of a cell, far from the base station. These UEs typically suffer from higher interference, lower signal strength, and increased power consumption, leading to lower throughput and higher call drop rates. Solving this issue is crucial for delivering QoS across the network. ◼ Reinforcement Learning for Uplink Power Control Uplink power control (UL-PC) is essential for balancing coverage and capacity in the uplink path. Traditional power control methods can be suboptimal, especially for cell edge UEs, causing high interference and poor performance. Reinforcement learning (RL) provides a dynamic approach to adjusting power levels based on real-time feedback from the network and the UEs. ◼ Implementation In RL-based UL-PC, the base station (gNB) acts as the RL agent, continuously adjusting the transmission power of UEs to optimize network performance. The RL agent receives state information, such as signal-to-noise ratio (SNR) and interference levels, and determines the best action (power adjustment) to maximize rewards, such as improved throughput and reduced interference. Random Forest for UE Classification Effective UL-PC requires accurate classification of UEs based on various factors like location, power headroom report (PHR), buffer status report (BSR), interference levels, and signal quality metrics (RSRP, SNR). Random forest, a robust machine learning algorithm, excels in handling such classification tasks. Accurate classification informs better power control strategies, enhancing overall network performance. Large Language Model for RL Reward Function Design An LLM can generate reward functions based on textual descriptions of the task, objectives, states, and actions. The LLM can refine these functions iteratively based on feedback from the RL agent's performance. LLMs reduce the need for manual reward function design, saving time and effort. Combining RL, random forest, and LLMs creates a powerful framework for optimizing mobile network performance at the cell edge: - UE Classification: Use a random forest model to classify UEs based on collected data. - Power Control Optimization: Implement RL to dynamically adjust UL-PC based on real-time feedback and UE classification. - Reward Function Design: Utilize LLMs to design and refine reward functions for the RL agent, ensuring optimal power control strategies. Ref: https://lnkd.in/e-U5XNY6 #RANOptimization #AIML #RAN #PowerControl #ReinforcementLearning #LLM

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The use of coherent transceiver technology helps edge networks span longer reaches with higher capacity, but it also comes with the trade-off of increased latency due to more signal processing from the DSP. What the different boundary conditions are and what it means for DSP building blocks is the topic of this weeks article. Enjoy the read. #dsp #latency #transceiver #photonics #ai #cluster #cloud #coherent #transceivers #effectphotonics

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Thanks to the surge in #AI demand, #Samsung and #SKHynix #HBM #capacity is said to be fully booked until next year, and have reportedly converted their #DRAM capacity to produce #HBM! According to the latest forecast by #Trendforce, the #HBM market is poised for robust growth, driven by significant pricing premiums and increased capacity needs for #AIchips. #HBM prices are expected to Increase by 5–10% in 2025.

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1200V 900A Hybrid module. With SiC SBD diode inside，the turn on switching loss is reduced to a very low level.

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Explore the key types of amplifiers used in sensor signal chains and their applications, from transimpedance amplifiers to charge and voltage amplifiers. Learn how they enhance performance and reliability in various sensor systems. [Read the full post on Linear Systems' page.](#) https://lnkd.in/diQtZ9VW

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SIM7912E-M2 is the LTE Cat 12 module which supports wireless communication modes of LTE-TDD/LTE-FDD/HSPA+. It supports maximum 600Mbps downlink rate and 150Mbps uplink rate. SIM7912E-M2 adopts M.2 form factor. It is easy for customers to integrate. SIM7912E-M2 integrates multiple satellite high accuracy positioning GNSS systems, with multiple built-in network protocols, supports drivers for main operation systems (USB driver for Windows, Linux and Android etc.) and software function, AT commands are compatible with SIM7912X-M2 series modules. Meanwhile SIM7912E-M2 integrates main industrial standard interfaces, with powerful expansibility, including abundant interfaces such as UART, USB, GPIO, which is suitable for main IoT applications such as telematics, surveillance devices, CPE, industrial routers, and remote diagnostics etc. #sim7912 #sim7912e #sim7812g #4g #cat12 #wireless #iot #lte #4glte #4gmodule #router #4grouter #cpe #gnss #gps

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On the #security front, issue #8 of 3GPP newsletter contains an article on the Security Assurance (#SCAS) specifications developed by SA WG3. Thanks to my colleagues in SA3, we have been prolific in creating Security Assurance specifications for all major EPC nodes, eNB (4G) and almost all 5G core network nodes. Theses specifications define the basic fundamental test cases which are are used in the GSMA NESAS certification program which are mandatory for the EU and many other regional #cyber-certification and compliance programs.

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Download the May-June 2024 issue of Microwaves & RF. Inside this issue, you'll find topics from IEEE MTT-S International Microwave Symposium (IMS), wireless #SoCs built for #energyharvesting, and #5G from companies like Spirent Communications, Silicon Labs, Samtec Inc, SiTime, and more! #MWRF

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TSMC and Cadence are collaborating on next-generation #AI-driven flows, including the Cadence Cerebrus™ Intelligent Chip Explorer, for design productivity and optimization and Pegasus™ Verification System for Physical verification Signoff. #Cadence #Signoff #PhysicalVerification #Design #FoundryCertified “We have a distinguished track record collaborating with TSMC to deliver a broad set of innovations across EDA, packaging and IP to accelerate system and semiconductor design and enable customers to achieve aggressive time-to-market goals. These new certified design flows and standardized solutions allow customers to confidently design for TSMC advanced nodes and usher in improved design efficiency and technological advancements,” said Chin-Chi Teng, SVP and GM, R&D, Cadence. Read the press release here: https://ow.ly/bTym50REHjG

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