“I worked with Parag for close to 3 years including in capacity of Manager and it was great working with him. Parag is passionate, enthusiastic and professional about his work. He is curious and likes challenges. It was a great pleasure working alongside with him on numerous projects”
Experience & Education
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SalVentureTech
View Parag’s full experience
See their title, tenure and more.
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Licenses & Certifications
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Mistake Proofing Six Sigma Training
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Issued -
Lean - Six Sigma Training
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Issued -
Patents
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Real Time Vehicle Communicator
Filed US 61/973, 727
Projects
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Bump Mapping (Graphics)
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Bump mapping on computer objects which added shades, bumps and color to the objects. Programming language used : C
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Digital Neural Network
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o Design of an artificial neural network comprising of digital neurons using standard cell libraries.
o Edges were detected while moving from top to bottom of a network.
o Implementation of design and layout was performed using Cadence(Schematic/Virtuoso) and simulation was done
using Hspice. -
Direct Digital Synthesizer
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o Variable frequency sine wave was generated using a direct digital synthesizer, which was designed using (High speed/low power 1.28Kbit SRAM, 16 bit Ladner Fischer adder, pipelined phase accumulator, DAC and registers).
o Design and layout was implemented using Cadence(Schematic/Virtuoso) and simulation was performed using
Nanosim. -
Path Tracking Robot
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Designed path tracking robot that made its way towards its destination avoiding obstacles. Programming language used : C
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Pipelined Processor
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o Simulated and verified the execution of a 5 stage pipelined processor to support in order execution of MIPS
instructions taking care of RAW and Branch hazards with both early as well as late branching.
o Simulation was performed using ePD Schematic capture.
o Design and verified in VHDL using Mentor Graphics’ Modelsim simulator. Implemented on Spartan 3E FPGA using
Xilinx ISE 9.1. -
Solid State Semiconductor Wafer Fabrication
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o Processed and fabricated 3” silicon wafer using 2.5 micron technology.
o Performed Lithography, Diffusion, Oxidation, Etching and Metallization processes.
o Finished wafers electrically tested for parameter extraction. -
SRAM DESIGN:
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o 64 Kbit Synchronous SRAM design which included the design of write and read control circuitry, row and column decoder(pre-decoding), column mux, sense amplifier and clock routing designs.
o Optimization using divided bit and word lines. Innovative power reduction techniques were also used.
o Layout of 1.28Kb also performed. Tools used were Cadence(Schematic/Virtuoso) and Nanosim
o Critical Static timing analysis performed. -
TOMASULO Processor
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o Designed the various parts of the processor which included - Dispatch Unit, Instruction Fetch Queue, Issue Queues
& Issue Unit.
o The processor used TOMASULO algorithm for dynamic scheduling of instructions.
o Design and verified in VHDL using Mentor Graphics’ Modelsim simulator. Implemented on Spartan 3E FPGA using
Xilinx ISE 9.1. -
TROY PROCESSOR
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o Processor core based on a pipelined architecture for Processing in Memory application.
o Fetches a 128 bit data field but is capable of operating on 8, 16, or 32 bit words.
o Verilog Behavioral modeling & Synthesis using Cadence tools.
o Includes stalling and forwarding logics. One of the best speeds achieved of 264MHz.
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