Mobashar Yazdani

Active in technology assessment and development and ecosystem generation which engineering and suppliers.

https://scholar.google.com/citations?user=DhVIV9sAAAAJ&hl=en

Extended the state of the art in DC DC conversion by working on STC Topology and promoting it to the industry. Got best paper award by IEEE

One of the biggest challenges today in datacenter computing is to utilize power in a manner proportional to the work delivered. While power supply conversion efficiency improvements may provide incremental benefits across a wide range of workloads, they will not effectively address the case of disproportionate power consumption during light load conditions. In this paper we present an overview of the problem space, discuss current practice and present some areas of opportunity to help make… Show more

One of the biggest challenges today in datacenter computing is to utilize power in a manner proportional to the work delivered. While power supply conversion efficiency improvements may provide incremental benefits across a wide range of workloads, they will not effectively address the case of disproportionate power consumption during light load conditions. In this paper we present an overview of the problem space, discuss current practice and present some areas of opportunity to help make energy proportionality a reality for large scale datacenter computing.

http://www.designcon.com/santaclara/scheduler/session/energy-proportional-power-management-for-datacenter-applications
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Compressive analysis and discussion on selection and validation for IP for ASICs/COT from Vendors. Focus on techniques for making sure the right vendors are chosen and IP can be developed and is validated for first time success.

The wide-word architecture was developed in HP Labs as the next generation CPU architecture and transferred to Intel as EPIC architecture. This type of architecture requires high speed, high bandwidth second level cache memory to support it. Since the efficiency and the flexibility of the cache line transaction in between the CPU and the memory control unit would greatly affect the overall system performance, those important cache data transferring functions such as byte write, bypass… Show more

The wide-word architecture was developed in HP Labs as the next generation CPU architecture and transferred to Intel as EPIC architecture. This type of architecture requires high speed, high bandwidth second level cache memory to support it. Since the efficiency and the flexibility of the cache line transaction in between the CPU and the memory control unit would greatly affect the overall system performance, those important cache data transferring functions such as byte write, bypass, compare and swap capabilities have to be included in the second level cache to achieve the optimal performance. One of the project goals within HP wide-word program was to design a 16 K/spl times/72 synchronous, pipelined smart cache SRAM which is capable of sending out data at a rate of 2.25 Gbyte data per second. Today this architecture is in the chiplets designed for high performance XPUs.

https://ieeexplore.ieee.org/document/520667 Show less