James Machiorletti

When adding stitching vias to a PCB, strategic placement is crucial. It's essential to position them around the edges of critical components, high-speed signal traces, and ground planes. This ensures effective shielding and enhanced signal integrity. The appropriate size and spacing of stitching vias are chosen based on your application's specific requirements and the PCB's material. #PCBdesign

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In the intricate world of PCB manufacturing, the significance of PCBA box build assembly cannot be overstated. It represents the final stage where various components, subassemblies, enclosures, and software/firmware integration come together to form a fully functional electronic device.

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Stitching vias, also known as via stitching, are a crucial design practice for PCBs. By placing a series of vias around the perimeter of a ground plane or signal trace, a continuous conductive path is created, connecting the top and bottom layers of the board. #PCBdesign #viastitching

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In this podcast Brad Griffin discusses signal and power integrity decision making. Discover how you can eliminate the back and forth between PCB designers and electrical engineers using new SI/PI methodologies. Listen to Episode 4 of I-Connect007's "On the Line With... Cadence" series now! https://bit.ly/3JRFlud #PCBDesign #Cadence

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High data rates and intricate network configurations can lead to signal integrity challenges in #AutomotiveEthernet. This article explores real-world issues and provides practical insights for identifying and debugging these problems using oscilloscopes. Read More Here: https://lcry.us/3JojkmF #SignalIntegrity #AutomotiveEngineering #Oscilloscopes

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Latest Podcast Episode: Empowering Electrical Engineers. Next on “PCB 3.0: A New Design Methodology—More Power to the EE,” we're discussing how to bring more "power" (and "signal”) to the electrical engineer with Supreeth Mannava, Cadence Design Systems. https://bit.ly/3QXBq34 What should manufacturers know? What does this mean for EEs and the new generation of designers? Listen to find out!

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Managing power is critical in chip design, but it's much more so when the power budgets extend into the kilowatt range. That was the focus of a recent panel at #61DAC, titled "Blackout - Managing kW Power Budgets," featuring industry leaders in IC design, EDA, IP, and system design. The discussion was both engaging and insightful, delving into the intricacies of power management in the high-performance and kW+ era. As HPC and AI workloads drive increased computing demands at an accelerating pace, design teams must adopt a multi-pronged approach to IC and systems power management for next-generation computing.   For those who missed the event, here are some key highlights from the panel: ● 𝐒𝐲𝐬𝐭𝐞𝐦 𝐚𝐧𝐝 𝐒𝐲𝐬𝐭𝐞𝐦-𝐨𝐟-𝐒𝐲𝐬𝐭𝐞𝐦 𝐂𝐨-𝐃𝐞𝐬𝐢𝐠𝐧: Understanding how incremental improvements contribute cumulatively across the entire design ecosystem. ● 𝐄𝐱𝐩𝐚𝐧𝐝𝐢𝐧𝐠 𝐒𝐢𝐥𝐢𝐜𝐨𝐧 𝐈𝐏’𝐬 𝐑𝐨𝐥𝐞: Examining how silicon IP is reshaping power consumption trajectories and its pivotal role in future advancements. ● 𝐍𝐞𝐱𝐭-𝐆𝐞𝐧, 𝐇𝐢𝐠𝐡-𝐃𝐞𝐧𝐬𝐢𝐭𝐲 𝐕𝐑𝐌𝐬: Investigating the expanded co-design possibilities of high-density VRMs for data centers and beyond. ● 𝟐.𝟓𝐃 𝐚𝐧𝐝 𝟑𝐃 𝐒𝐨𝐥𝐮𝐭𝐢𝐨𝐧𝐬: Addressing the nuanced thermal and power design challenges posed by these emerging technologies.   Thank you to our panelists and moderator:   Mo Faisal - Movellus Inc. Joseph C. Davis - Design with Calibre Trey Roessig - Empower Semiconductor Hans Yeager - Tenstorrent Moderated by: Ed Sperling - Semiconductor Engineering

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#ConsumerElectronics #Embedded   Fuel gauging is a critical component of today’s rechargeable embedded devices. In this episode of Chalk Talk, Amelia Dalton and Robin Saltnes of Nordic Semiconductor explore the variety of benefits that Nordic Semiconductor’s nPM1300 PMIC brings to rechargeable embedded devices, the details of the fuel gauge system at the heart of this solution and … Read More → "Ultra-low Power Fuel Gauging for Rechargeable Embedded Devices – Nordic Semiconductor and Mouser" https://lnkd.in/gdhWd2Vx

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With a wide operating range of 30 VDC to 550 VDC input, this automotive power supply design kit uses an AEC-Q100 certified LinkSwitch-TN2Q for a 9.75 W non-isolated nominal output voltage of 15 V at 650 mA (RDK-707Q). https://okt.to/dm0Oow #electricvehicles #powerelectronics

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Tired of tedious DC I-V and C-V testing? 🙄 Testing power semiconductors shouldn't be a frustrating, time-consuming, and error-prone process. This application note offers a solution that will revolutionize your testing process: 📌 Minimize connection changes, simplifying your setup. 📌 Reduce user error, improving accuracy. 📌 Streamline testing, saving you valuable time. Don't let cumbersome testing procedures hold you back. Join the revolution and embrace a smarter approach to semiconductor testing. 💡 Read the App Note here ➡️ https://lnkd.in/d7wjE4cN #Semiconductor #SemiconductorIndustry #TestEngineer

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10 high-speed #PCBlayout design rules 1. Have a common ground plane right below the signal traces 2. Ensure adequate spacing between vias to avoid hotspots 3. Place vias symmetrically to eliminate impedance discontinuities 4. Maintain minimum bends while routing 5. Add serpentines to length match the traces 6. Maintain at least 3W spacing between the signal traces to minimize crosstalk 7. Implement daisy chain routing to avoid long stubs 8. Do not place components and vias between differential pairs 9. Design differential pairs with symmetrical paths and keep signals in parallel 10. Route differential signals on the same layer -- Read the article for more. -- Share this post with PCB designers and engineers. #ElectronicsDesign #SignalIntegrity #ElectricalEngineering

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#Needed #Quickly! #Semiconductor #Experts By— Surajeet Das Gupta | May 01, 2024 ||Semiconductor makers #need #thousands of #engineers and #technicians, and though #India 🇮🇳 has one of the largest pool of engineers in the #world, they do not have experience in the semiconductor #manufacturing space.|| The government, based on feedback from semiconductor companies operating in India, expects hundreds to thousand-odd Indian engineers to return from Southeast Asia and the United States to participate in the country's high-tech manufacturing revolution. "Nearly 20 to 25 per cent of the senior talent in the semiconductor manufacturing industry globally are Indians. We expect many of them to come back to India," says #Communications, #IT, and Railway #Minister #AshwiniVaishnaw. According to a top official in the #ministry of #electronics and #information #technology (#Meity), the #engineers who have decided to #return to #India from the #US are younger, while those from #Taiwan, #Singapore, and #Malaysia are generally over 45 years and with more experience. The official says that in the #US, the senior and therefore older semiconductor professionals whose families have settled down do not want to move out. But in Southeast Asia, many want to return home and are looking for opportunities. The response to the Tata group's recruitment drive in Taiwan for its OSAT (#outsourced #semiconductor #assembly and #test) and #fabrication (#fab) plant is a case in point, says the Meity official. #Tata #Electronics held roadshows in Taiwan's chip manufacturing centre of Hsinchu to attract professionals with 5 to 18 years of experience in yield, automation and equipment, among other fields. The company has tied up with Taiwanese chipmaker PSMC for technology, and its engineers may undergo training with the company. #AppliedMaterials #Applied #Materials #ATMP (#assembly, #testing, #marking, and #packing) #plant #OSAT #PSMC #technology #makeinindia India Semiconductor Mission Semiconductor Nation - Campus Connect #Details: ⤵️ https://lnkd.in/gyhRsfBk

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ESD Protection: Alpha and Omega Semiconductor's Game-Changing Innovation! Alpha & Omega Semiconductor (AOS) has unveiled the AOZ8S205BLS Series, a groundbreaking line of ultra-low capacitance TVS diodes. This innovation is set to redefine ESD protection for high-speed interfaces, enhancing device reliability and aligning with the demands of advanced electronic systems. Why It Matters: 🔹 Ultra-Low Capacitance: At just 0.075pF, AOS’s new series meets the critical needs of high-speed data and antenna-based applications, crucial for devices like USB4 v2.0 and Thunderbolt 5. 🔹 High-Trigger Voltage: Ensures robust protection against electrostatic discharges without compromising signal integrity, a pivotal enhancement over traditional ESD solutions. Strategic Impact: 💡 AOS is poised to set new industry standards, potentially reshaping market dynamics as competitors and partners alike might seek to either collaborate or innovate parallel technologies. 💡 The shift towards more efficient ESD protection could expand the market for advanced TVS diodes, influencing customer expectations and pushing for higher performance benchmarks. Investor Insights: 💼 Market Leadership Potential: AOS’s pioneering technology positions it as a leader in the TVS diode market, suggesting a promising avenue for growth and influence. 💼 Competitive Advantage: The unique features of the AOZ8S205BLS Series provide AOS with a distinct competitive edge, likely boosting adoption rates among major electronics manufacturers and driving revenue growth. 💼 Industry Impact: With the potential to set new standards in ESD protection, AOS could become a key player in the semiconductor industry, making it an attractive option for investors looking for exposure to innovative technology sectors. As we witness this exciting development, the implications for the semiconductor industry and beyond are profound. For those keen on the intersection of innovation and market leadership, AOS represents a compelling narrative worth following. Read More: https://lnkd.in/gWjXTnHw #AlphaOmegaSemiconductor #Semiconductors #Innovation #Technology #ESDProtection #InvestmentOpportunity #MarketLeadership #AOZ8S205BLS #TechNews #BusinessStrategy

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🚀 **Insights from Chip Designer Jim Keller on Nvidia's Blackwell Interconnect Costs** 🔍 I recently read a fascinating article where chip designer Jim Keller, known for his work at AMD, Tesla, and Intel, criticized Nvidia's Blackwell interconnect costs. Here are some key takeaways from the article: - **High Costs of Interconnects**: Keller highlighted that the interconnects in Nvidia's Blackwell chips might be significantly increasing production costs. This is due to the complex structure and high precision required. - **Impact on Industry Trends**: He suggested that these high costs could influence broader trends in the semiconductor industry, potentially leading to changes in chip design approaches. - **Efficiency vs. Performance**: Keller's comments raise an important question about the balance between achieving high performance and managing production costs. He emphasized the need for a holistic view when designing cutting-edge chips. - **Potential Solutions**: One suggestion was exploring different architectures or interconnect technologies to reduce costs without sacrificing performance. Keller's remarks indicate there's room for innovation in this area. What do you think about the cost-performance balance in chip design? How should companies like Nvidia navigate this challenge? Let's discuss in the comments below! 💬 📢 Join our VLSI Connect News channel on Telegram: https://lnkd.in/gk4gyWvt 📰 Stay updated with VLSI Connect News on LinkedIn: https://lnkd.in/g5aYa3Cp 🔗 Explore more on our website: https://vlsiconnect.com/ 🎧 Listen to our Daily news on Spotify: https://lnkd.in/gUGv4GhP https://lnkd.in/g86yePB2

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