Dr Shreekant (Ticky) Thakkar

أبو ظبي الإمارات العربية المتحدة معلومات الاتصال
٧ آلاف متابع أكثر من 500 زميل

انضم لعرض الملف الشخصي

نبذة عني

Throughout an eventful career, I have been regarded as someone who not only defines…

مقالات Dr Shreekant (Ticky)

عرض كل المقالات

النشاط

انضم الآن لعرض كل النشاط

الخبرة والتعليم

  • Technology Innovation Institute

عرض خبرة Dr Shreekant (Ticky) الكاملة

تعرّف على المسمى الوظيفي للأشخاص ومعدل بقائهم في العمل والكثير غير ذلك.

أو

بالنقر على الاستمرار للانضمام أو تسجيل الدخول، فأنت توافق على اتفاقية المستخدم واتفاقية الخصوصية وسياسة ملفات تعريف الارتباط على LinkedIn.

المنشورات

  • “Emergence of the Digital Office; Connected Workforce”

    Cisco Systems, Book [Invited] [Intel VPro Vision/Product]

  • “CTO Mobile Platform Group”

    Intel – Position Paper

  • “Second-Generation Intel® Centrino™ Mobile Technology Platform”

    Journal Paper [Intel Reviewed] [Intel Product]

  • Battery Life Challenges on Future Mobile Platforms, IEEE Symposium on Low Power Electronics and Design

    Keynote Talk, (A1) [Invited] [Intel Product]

  • “Programmer’s Guide for Internet Streaming SIMD Extensions”

    Book [Intel Product]

  • “Mobile PC Platforms Enabled with Intel® Centrino™ Mobile Technology”

    Journal Paper, Intel Technology Journal [Intel Reviewed] [Intel Product]

    مؤلفون آخرون
    • Gordon Chin
    • Sanjiv Desai
    • Eric Distefano
    • Krishnan Ravichandran
  • "Internet Streaming SIMD Extensions"

    Computer, IEEE Computer Society Press, Vol. 32, no. 12, pp. 26-34, (A2) [Reviewed] [Intel Product]

    مؤلفون آخرون
    • Tom Huff
  • “The Internet Streaming SIMD Extensions”

    Journal Paper, Intel Technology Journal, Intel Technology Journal [Intel Reviewed] [Intel Product]

    مؤلفون آخرون
    • Tom Huff
  • “Multiprocessor Validation of the Pentium Pro”

    Computer, IEEE Computer Society Press, Vol. 29, Issue 11, (A3) [Reviewed] [Intel Product]

    مؤلفون آخرون
    • Deborah T. Marr
    • Subramanian Natarajan
    • Richard Zucker
  • Multiprocessor Validation of the Pentium® Pro Microprocessor

    COMPCON: 395-400 [Reviewed] [Intel Product]

    مؤلفون آخرون
    • Deborah T. Marr
    • Richard Zucker
  • Editors: “Workshop on Scalable Shared Memory Multiprocessors”

    Kluwer Academic Publishers, Seattle/Boston, pp 207-218, May 1992

  • Tuning a Parallel Database Algorithm on a Shared-memory Multiprocessor

    Softw., Pract. Exper. 22(7): 495-517 (A5) [Reviewed]

    مؤلفون آخرون
    • Goetz Graefe
  • “Symbolic Methods in Numerical Optimization”

    Technical Report, Oregon State University, (A6)

    مؤلفون آخرون
    • Wang Po
    • Theodore G. Lewis
    • Giuseppe Cerbone
    • Thomas G. Dietterich
  • Editors: “Scalable Shared-Memory Multiprocessors”

    Kluwer Academic Publisher, Norwell, Mass.

    مؤلفون آخرون
    • Michel Dubois
  • “Performance of Parallel Applications on a Shared-Memory Multiprocessor System”

    Parallel Computer Systems, ACM Press, November 1990 (A7)

  • "Performance of an OLTP Application on Symmetry Multiprocessor System"

    In Proceedings of the 17th Annual International Symposium on Computer Architecture, ACM SIGARCH Computer Architecture News, ACM Press, Vol. 18, No. 3, P 228-238 (A8) [Reviewed] [Sequent Product]

    مؤلفون آخرون
    • Mark Sweiger
  • “Guest Editor’s Introduction: Cache Architectures I Tightly Coupled Multiprocessors”

    Computer, IEEE Computer Society Press, Volume 23, Issue 6 (special issue)

    مؤلفون آخرون
    • Michel Dubois
  • “New Directions in Scalable Shared-Memory Multiprocessor Architectures”

    IEEE Computer, IEEE Computer Society Press, Vol. 23, Issue 6, pp71-83 (A9) [Reviewed]

    مؤلفون آخرون
    • Michel Dubois
    • Anthony T. Laundrie
    • Gurindar S. Sohi
    • David V. James
    • Stein Gjessing
    • Manu Tapar
    • Bruce Delagi
    • Michael Carlton
    • Alvin Despain
  • Synchronization Algorithms for Shared-Memory Multiprocessors

    IEEE Computer 23(6): 60-69 [Reviewed] (A4)

    مؤلفون آخرون
    • Gary Graunke
  • “Guest Editor’s Introduction: Parallel Programming; Harnessing the Hardware”

    IEEE Software, IEEE Computer Society Press, Vol. 6, Issue 4

  • "Performance of Symmetry Multiprocessor System; Cache and Interconnect Architectures in Multiprocessors"

    Kluwer Academic Publishers, pp52-82, Boston (A10) [Sequent Product]

  • “Guest Editor’s Introduction: Parallel Programming Issues and Questions”

    IEEE Software, IEEE Computer Society Press, Vol. 5, Issue 1

  • “Programming Three Parallel Computers”

    IEEE Software, IEEE Computer Society Press, Vol. 5, Issue 1 (A11) [Reviewed]

    مؤلفون آخرون
    • Marta Kallstrom
  • “The Balance Multiprocessor System”

    IEEE Micro, IEEE Computer Society Press, Vol. 8, Issue 1 (A13) [Reviewed] [Sequent Product]

    مؤلفون آخرون
    • Paul Gifford
  • “The Symmetry Multiprocessor System”

    Proc. International Conf. Parallel Processing, Pennsylvania State University Press, University Park, Pa., pp303-310 (A12) [Reviewed] [Sequent Product]

  • “VLSI Assist for a Multiprocessor”

    EEE Computer Society Press, ACM Press, Vol. 15, 22, 21, Issue 5, 10, 4 (A14) [Reviewed] [Sequent Product]

    ACM SIGARCH Computer Architecture News , ACM SIGPLAN Notices , ACM SIGOPS Operating Systems Review (ASPLOS), Proceedings of the second international conference on Architectural support for programming languages and operating systems ASPLOS-II

    مؤلفون آخرون
    • Bob Beck
    • Bob Kasten
  • Editor, “Selected Reprints on Dataflow and Reduction Architectures”

    IEEE Computer Society Press, pp 79-101, June 1987 Book

  • Experience with Three Parallel Programming Systems

    COMPCON: 344-351

    مؤلفون آخرون
    • Marta Kallstrom
  • Instruction Fetch Unit for a Graph Reduction Machine,

    Proceedings of 13th Annual Conference on Computer Architecture, pp82-91, June 1986, Tokyo, Japan [Reviewed] (A16)

    مؤلفون آخرون
    • William Hostmann
  • “A High-Performance Memory Management Scheme”

    Computer, IEEE Computer Society Press, May 1986 (A17) [Reviewed]

    مؤلفون آخرون
    • Alan E. Knowles
  • “The Cognitive Architecture Project”

    ACM SIGARCH Computer Architecture News, ACM Press, Vol. 14, Issue 1, pp9-21, January 1986 (A15)

    مؤلفون آخرون
    • Dan Hammerstrom
    • David Maier

براءات الاختراع

  • 6,263,426 Conversion from packed floating point data to packed 8-bit integer data in different architectural registers

    US 6,263,426

  • Advanced graphics port (AGP) display driver with restricted execute mode for transparently transferring textures to a local texture cache

    US 6,295,068

  • Apparatus and method for multiplexing bi-directional data onto a low pin count bus between a host CPU and co-processor

    US 6,434,650

  • Attestation key memory device and bus

    US 7,013,481

  • Attestation key memory device and bus

    US 7,194,634

  • Cache pollution avoidance instructions

    US 6,275,904

  • Computer system with detachable display

    US 7,206,196

  • Controlling access to multiple isolated memories in an isolated execution environment

    US 6,678,825

  • Controlling access to multiple memory zones in an isolated execution environment

    US 6,934,817

  • Controlling access to multiple memory zones in an isolated execution environment

    US 6,633,963

  • Controlling accesses to isolated memory using a memory controller for isolated execution

    US 6,795,905

  • Conversion between packed floating point data and packed 32-bit integer data in different architectural registers

    US 6,266,769

  • Conversion between packed floating point data and packed 32-bit integer data in different architectural registers

    US 6,502,115

  • Conversion from packed floating point data to packed 16-bit integer data in different architectural registers

    US 6,247,116

  • Conversion from packed floating point data to packed 8-bit integer data in different architectural registers

    US 6,480,868

  • Convertible and detachable laptops

    US 7,251,127

  • Convertible and detachable laptops

    US 6,775,129

  • Data conversion between floating point packed format and integer scalar format

    US 6,292,815

  • Digital watermarks with values derived from remote platforms

    US 7,111,167

  • Efficient saving and restoring state in task switching

    US 6,898,700

  • Executing isolated mode instructions in a secure system running in privilege rings

    US 6,507,904

  • Executing partial-width packed data instructions

    US 6,970,994

  • Executing partial-width packed data instructions

    US 6,970,994

  • Executing partial-width packed data instructions

    US 7,467,286

  • Extended stand computer system with non-retractable carrying handle

    US 7,259,750

  • Extended stand computer system with retractable keyboard

    US 7,042,712

  • Fault-tolerant boot strap mechanism for a multiprocessor system

    US 5,724,527

  • File checking using remote signing authority via a network

    US 7,096,497

  • Generating a key hieararchy for use in an isolated execution environment

    US 6,760,441

  • Generating isolated bus cycles for isolated execution

    US 7,111,176

  • Instruction set extension using prefixes

    US 6,014,735

  • Integrating non-peripheral component interconnect (PCI) resource into a personal computer system

    US 8,010,731

  • Integrating non-peripheral component interconnect (PCI) resources into a computer system

    US 8,745,303

  • Integrating non-peripheral component interconnect (PCI) resources into a personal computer system

    US 8,463,975

  • Integrating non-peripheral component interconnect (PCI) resources into a personal computer system

    US 8,209,456

  • Integrating non-peripheral component interconnect (PCI) resources into a personal computer system

    US 7,783,819

  • Managing a secure environment using a chipset in isolated execution mode

    US 7,085,935

  • Managing a secure environment using a chipset in isolated execution mode

    US 7,013,484

  • Managing a secure platform using a hierarchical executive architecture in isolated execution mode

    US 6,941,458

  • Managing a secure platform using a hierarchical executive architecture in isolated execution mode

    US 6,957,332

  • Managing a secure platform using a hierarchical executive architecture in isolated execution mode

    US 6,941,458

  • Managing a secure platform using a hierarchical executive architecture in isolated execution mode

    US 6,957,332

  • Managing accesses in a processor for isolated execution

    US 7,089,418

  • Memory attribute palette

    US 5,946,713

  • Method and apparatus for a power-efficient framework to maintain data synchronization of a mobile personal computer to simulate a connected scenario

    US 8,019,370

  • Method and apparatus for a power-efficient framework to maintain data synchronization of a mobile personal computer to simulate a connected scenario

    US 8,224,402

  • Method and apparatus for a power-efficient framework to maintain data synchronization of a mobile personal computer to simulate a connected scenario

    US 7,725,093

  • Method and apparatus for a power-efficient framework to maintain data synchronization of a mobile personal computer to simulate a connected scenario

    US 9,395,806

  • Method and apparatus for accessing more than 4 Gigabytes of physical memory with 4-byte table entries

    US 6,289,431

  • Method and apparatus for caching memory content on a computing system to facilitate instant-on resuming from a hibernation state

    US 7,594,073

  • Method and apparatus for converting data format to a graphics card

    US 6,288,723

  • Method and apparatus for efficient vertical SIMD computations

    US 6,115,812

  • Method and apparatus for floating point operations and format conversion operations

    US 7,216,138

  • Method and apparatus for moving select non-contiguous bytes of packed data in a single instruction

    US 6,052,769

  • Method and apparatus for parallel conversion of color values from a single precision floating point format to an integer format

    US 5,995,122

  • Method and apparatus for performing cache segment flush and cache segment invalidation operations

    US 6,978,357

  • Method and apparatus for performing integer operations in response to a result of a floating point operation

    US 6,317,824

  • Method and apparatus for staggering execution of a single packed data instruction using the same circuit

    US 6,694,426

  • Method and apparatus for staggering execution of a single packed data instruction using the same circuit

    US 6,230,257

  • Method and apparatus for staggering execution of a single packed data instruction using the same circuit

    US 6,687,810

  • Method and apparatus for staggering execution of an instruction

    US 7,366,881

  • Method and apparatus for staggering execution of an instruction

    US 6,425,073

  • Method and system for implementing control signals on a low pin count bus

    US 6,463,494

  • Method and system for implementing control signals on a low pin count bus

    US 6,463,494

  • Method and system for scrubbing an isolated area of memory after reset of a processor operating in isolated execution mode if a cleanup flag is set

    US 6,754,815

  • Multi-element operand sub-portion shuffle instruction execution

    US 7,155,601

  • Pen-based computing system with a releasable socket connector for connecting a base unit to a tablet unit

    US 6,780,019

  • Platform and method for generating and utilizing a protected audit log

    US 7,073,071

  • Platform and method for issuing and certifying a hardware-protected attestation key

    US 6,996,710

  • Platform and method for remote attestation of a platform

    US 6,990,579

  • Platform and method for remote attestation of a platform

    US 7,254,707

  • Processor unique processor number feature with a user controllable disable capability

    US 6,289,459

  • Protecting software environment in isolated execution

    US 7,082,615

  • Protecting software environment in isolated execution

    US 7,380,278

  • Protecting software environment in isolated execution

    US 7,082,615

  • Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC)

    US 9,547,618

  • Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC)

    US 8,205,029

  • Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC)

    US 8,037,230

  • Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC)

    US 8,433,841

  • Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC)

    US 7,861,027

  • Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC)

    US 8,751,722

  • Providing information to a communications device

    US 6,883,019

  • Resetting a processor in an isolated execution environment

    US 6,769,058

  • Staggering execution of a single packed data instruction using the same circuit

    US 6,925,553

  • Synchronization of weakly ordered write combining operations using a fencing mechanism

    US 6,073,210

  • System and method for performing an intra-add operation

    US 6,211,892

  • System for reducing number of opcodes required in a processor using an instruction format including operation class code and operation selector code fields

    US 6,185,670

  • System, apparatus and method for integrating non-peripheral component interconnect (PCI) resources into a personal computer system

    US 9,600,433

الدورات التعليمية

  • Emotional Intelligence ▪ StrengthsFinder, HP

    -

  • Executive Coach, Leadership for Extraordinary Results, Intel University

    -

  • Possibility Thinking, Situational Leadership, Intel University

    -

المشروعات

  • Industry Firsts:

    -

    • Industry's first large (32-way) shared memory multiprocessor and mainstream (4-way) integrated server platforms.
    • Industry's first under ½" laptop, with longer battery life (> 4hrs) & weight under 4lbs; first generation of Centrino platform.
    • Industry’s first mobile benchmarking standard leadership through work in power and performance tuning of Mobile platforms.
    • Industry’s first All-in-One (AIO) Computers, Convertible-detachable Laptops, and IPAD-like tablets wining industry…

    • Industry's first large (32-way) shared memory multiprocessor and mainstream (4-way) integrated server platforms.
    • Industry's first under ½" laptop, with longer battery life (> 4hrs) & weight under 4lbs; first generation of Centrino platform.
    • Industry’s first mobile benchmarking standard leadership through work in power and performance tuning of Mobile platforms.
    • Industry’s first All-in-One (AIO) Computers, Convertible-detachable Laptops, and IPAD-like tablets wining industry awards.
    • Industry’s first Extended Battery Life Working Group to drive ecosystem to deliver lower power components (e.g., displays).
    • Industry’s first Context Aware service, connecting consumer behavior and user experience.

  • Key Leadership Contributions

    -

    • Drove new capabilities for HP devices; defined and built new capabilities such as Privacy screen and HP’s Ambient Computing (AC), delivering differentiation with execution and delivery of initiatives like HP's Office, Home, and Retail of the Future!
    • Designed/ executed Intel Xeon product, enabling businesses to make better, faster decisions with, real-time data analytics, big data insight, and scalable productivity using Xeon's cloud computing virtualization, reliability, and…

    • Drove new capabilities for HP devices; defined and built new capabilities such as Privacy screen and HP’s Ambient Computing (AC), delivering differentiation with execution and delivery of initiatives like HP's Office, Home, and Retail of the Future!
    • Designed/ executed Intel Xeon product, enabling businesses to make better, faster decisions with, real-time data analytics, big data insight, and scalable productivity using Xeon's cloud computing virtualization, reliability, and responsiveness.
    • Secured Intel’s 98% market share in Thin and Notebook platforms, cloud computing, and mainstream data center technologies, fueling billions of dollars in new annual revenue. Called the "Father of Intel Centrino and Atom Platforms".
    • Led design, development, and delivery of highly successful products for Intel, including Core and Intel Atom (Mobile Computing) platforms; contributed to industry’s mobile benchmarking standard, creating multibillion-dollar revenue streams.
    • Career record of building and leading highly regarded, inspired, motivated and diverse teams. Identifies future leaders and mentors staff members to roles of greater responsibility, and empowers individuals to excel.
    • Architected Intel’s Smartphone and Tablet platforms and successfully delivered technologies that trickled up Core platforms.

التكريمات والمكافآت

  • Awards & Recognition:

    -

    Recognized with multiple Intel Achievement Awards (IAA), the company’s highest honor for:
    • Centrino Platform delivering 4hrs of Battery Life, and Wireless Connectivity
    • Development of Intel’s mobile benchmarking standard and leadership for Notebook platforms
    • Design and delivery of Intel’s 1st-ever Notebook / Mobile concept program
    • Development of fine-grain power management
    • Development of Mobile Atom platforms

    Winner of multiple BusinessWeek / Industrial Design…

    Recognized with multiple Intel Achievement Awards (IAA), the company’s highest honor for:
    • Centrino Platform delivering 4hrs of Battery Life, and Wireless Connectivity
    • Development of Intel’s mobile benchmarking standard and leadership for Notebook platforms
    • Design and delivery of Intel’s 1st-ever Notebook / Mobile concept program
    • Development of fine-grain power management
    • Development of Mobile Atom platforms

    Winner of multiple BusinessWeek / Industrial Design Association Gold and Bronze Awards for Intel’s Mobile concepts
    Multiple divisional awards for creation of Mini PC, Atom Platform, Graphics & Media instruction set, Graphics accelerator interface, Security & Virtualization capabilities, Xeon MP platform and winning customer designs
    Winner of Intel’s highest awarded patents Award in a single year
    Recognized by major customers for outstanding work and contributions to product innovation

اللغات

  • English

    إجادة كاملة

  • Swahili

    مستوى إجادة محدود

  • Gujarati

    مستوى إجادة محدود

التوصيات المستلمة

17شخصا قدموا توصية لـDr Shreekant (Ticky)

انضم الآن لعرض

المزيد من أنشطة Dr Shreekant (Ticky)

عرض ملف Dr Shreekant (Ticky) الشخصي الكامل

  • مشاهدة الأشخاص المشتركين الذين تعرفهم
  • تقديم تعارف
  • تواصل مع Dr Shreekant (Ticky) مباشرة
انضم لعرض الملف الشخصي الكامل

ملفات شخصية أخرى مشابهة

اكتسب مهارات جديدة من خلال هذه المواد الدراسية